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Stefan Roese5e7abce2010-09-11 09:31:43 +02001/*
2 * (C) Copyright 2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese5e7abce2010-09-11 09:31:43 +02006 */
7
8#ifndef _PPC440GX_H_
9#define _PPC440GX_H_
10
11#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
12
13/*
14 * Some SoC specific registers (not common for all 440 SoC's)
15 */
Stefan Roese5e7abce2010-09-11 09:31:43 +020016
Stefan Roese550650d2010-09-20 16:05:31 +020017/* Memory mapped register */
18#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* Internal Peripherals */
19
20#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
21#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
22
23#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
24
25/* SDR's */
Stefan Roese5e7abce2010-09-11 09:31:43 +020026#define SDR0_PCI0 0x0300
27
28#define SDR0_SDSTP2 0x4001
29#define SDR0_SDSTP3 0x4003
30
31#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
32#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
33
34#define SDR0_PFC1_EPS_DECODE(n) ((((u32)(n)) >> 22) & 0x07)
35#define SDR0_PFC1_CTEMS_MASK (0x80000000 >> 11)
36#define SDR0_PFC1_CTEMS_EMS 0x00000000
37#define SDR0_PFC1_CTEMS_CPUTRACE (0x80000000 >> 11)
38
39#define SDR0_MFR_ECS_MASK 0x10000000
40
41#define SDR0_SRST_DMC 0x00200000
42
43#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
44#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
45#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
46#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
47#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
48#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
49#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
50#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
51#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
52
53#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
54#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
55#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
56#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
57#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
58#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
59
60#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
Mike Williams16263082011-07-22 04:01:30 +000061#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
Stefan Roese5e7abce2010-09-11 09:31:43 +020062#define PRADV_MASK 0x07000000 /* Primary Divisor A */
63#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
64#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
65
66/* Strap 1 Register */
67#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
68#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
69#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
70#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
Mike Williams16263082011-07-22 04:01:30 +000071#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
Stefan Roese5e7abce2010-09-11 09:31:43 +020072#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
73#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
74#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
75#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
76#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
77#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
78#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
79#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
80#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
81#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
82#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
83#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
84#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
85
86#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
87#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
88
89#endif /* _PPC440GX_H_ */