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wdenkc6097192002-11-03 00:24:07 +00001/*
stroese0621f6f2004-12-16 18:43:13 +00002 * (C) Copyright 2001-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/processor.h>
27#include <command.h>
28
29/* ------------------------------------------------------------------------- */
30
31#ifdef FPGA_DEBUG
32#define DBG(x...) printf(x)
33#else
34#define DBG(x...)
35#endif /* DEBUG */
36
37#define MAX_ONES 226
38
wdenkc6097192002-11-03 00:24:07 +000039#ifdef CFG_FPGA_PRG
40# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
41# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */
42# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */
43# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */
44# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */
45#else
46# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
47# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
48# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
49# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
50# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
51#endif
52
53#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
54#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
55#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
56
stroese0621f6f2004-12-16 18:43:13 +000057#ifndef SET_FPGA
58# define SET_FPGA(data) out32(GPIO0_OR, data)
59#endif
wdenkc6097192002-11-03 00:24:07 +000060
stroese0621f6f2004-12-16 18:43:13 +000061#ifdef FPGA_PROG_ACTIVE_HIGH
62# define FPGA_PRG_LOW FPGA_PRG
63# define FPGA_PRG_HIGH 0
64#else
65# define FPGA_PRG_LOW 0
66# define FPGA_PRG_HIGH FPGA_PRG
67#endif
68
69#define FPGA_CLK_LOW 0
70#define FPGA_CLK_HIGH FPGA_CLK
71
72#define FPGA_DATA_LOW 0
73#define FPGA_DATA_HIGH FPGA_DATA
74
75#define FPGA_WRITE_1 { \
76 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
77 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \
78 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \
79 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
wdenkc6097192002-11-03 00:24:07 +000080
81#define FPGA_WRITE_0 { \
stroese0621f6f2004-12-16 18:43:13 +000082 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
83 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \
84 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \
85 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
86
87#ifndef FPGA_DONE_STATE
88# define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE)
89#endif
90#ifndef FPGA_INIT_STATE
91# define FPGA_INIT_STATE (in32(GPIO0_IR) & FPGA_INIT)
92#endif
wdenkc6097192002-11-03 00:24:07 +000093
94
95static int fpga_boot(unsigned char *fpgadata, int size)
96{
97 int i,index,len;
98 int count;
99#ifdef CFG_FPGA_SPARTAN2
100 int j;
101#else
102 unsigned char b;
103 int bit;
104#endif
105
106 /* display infos on fpgaimage */
107 index = 15;
108 for (i=0; i<4; i++)
109 {
110 len = fpgadata[index];
111 DBG("FPGA: %s\n", &(fpgadata[index+1]));
112 index += len+3;
113 }
114
115#ifdef CFG_FPGA_SPARTAN2
116 /* search for preamble 0xFFFFFFFF */
117 while (1)
118 {
119 if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
wdenk8bde7f72003-06-27 21:31:46 +0000120 (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
121 break; /* preamble found */
wdenkc6097192002-11-03 00:24:07 +0000122 else
wdenk8bde7f72003-06-27 21:31:46 +0000123 index++;
wdenkc6097192002-11-03 00:24:07 +0000124 }
125#else
126 /* search for preamble 0xFF2X */
127 for (index = 0; index < size-1 ; index++)
128 {
129 if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30))
130 break;
131 }
132 index += 2;
133#endif
134
135 DBG("FPGA: configdata starts at position 0x%x\n",index);
136 DBG("FPGA: length of fpga-data %d\n", size-index);
137
138 /*
139 * Setup port pins for fpga programming
140 */
stroese0621f6f2004-12-16 18:43:13 +0000141#ifndef CONFIG_M5249
stroesec231d002003-05-23 11:32:53 +0000142 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
143 out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
stroese0621f6f2004-12-16 18:43:13 +0000144#endif
145 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */
wdenkc6097192002-11-03 00:24:07 +0000146
stroese0621f6f2004-12-16 18:43:13 +0000147 DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
148 DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
wdenkc6097192002-11-03 00:24:07 +0000149
150 /*
151 * Init fpga by asserting and deasserting PROGRAM*
152 */
stroese0621f6f2004-12-16 18:43:13 +0000153 SET_FPGA(FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */
wdenkc6097192002-11-03 00:24:07 +0000154
155 /* Wait for FPGA init line low */
156 count = 0;
stroese0621f6f2004-12-16 18:43:13 +0000157 while (FPGA_INIT_STATE)
wdenkc6097192002-11-03 00:24:07 +0000158 {
159 udelay(1000); /* wait 1ms */
160 /* Check for timeout - 100us max, so use 3ms */
161 if (count++ > 3)
wdenk8bde7f72003-06-27 21:31:46 +0000162 {
163 DBG("FPGA: Booting failed!\n");
164 return ERROR_FPGA_PRG_INIT_LOW;
165 }
wdenkc6097192002-11-03 00:24:07 +0000166 }
167
stroese0621f6f2004-12-16 18:43:13 +0000168 DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
169 DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
wdenkc6097192002-11-03 00:24:07 +0000170
171 /* deassert PROGRAM* */
stroese0621f6f2004-12-16 18:43:13 +0000172 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */
wdenkc6097192002-11-03 00:24:07 +0000173
174 /* Wait for FPGA end of init period . */
175 count = 0;
stroese0621f6f2004-12-16 18:43:13 +0000176 while (!(FPGA_INIT_STATE))
wdenkc6097192002-11-03 00:24:07 +0000177 {
178 udelay(1000); /* wait 1ms */
179 /* Check for timeout */
180 if (count++ > 3)
wdenk8bde7f72003-06-27 21:31:46 +0000181 {
182 DBG("FPGA: Booting failed!\n");
183 return ERROR_FPGA_PRG_INIT_HIGH;
184 }
wdenkc6097192002-11-03 00:24:07 +0000185 }
186
stroese0621f6f2004-12-16 18:43:13 +0000187 DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
188 DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
wdenkc6097192002-11-03 00:24:07 +0000189
190 DBG("write configuration data into fpga\n");
191 /* write configuration-data into fpga... */
192
193#ifdef CFG_FPGA_SPARTAN2
194 /*
195 * Load uncompressed image into fpga
196 */
197 for (i=index; i<size; i++)
198 {
199 for (j=0; j<8; j++)
wdenk8bde7f72003-06-27 21:31:46 +0000200 {
201 if ((fpgadata[i] & 0x80) == 0x80)
wdenkc6097192002-11-03 00:24:07 +0000202 {
wdenk8bde7f72003-06-27 21:31:46 +0000203 FPGA_WRITE_1;
wdenkc6097192002-11-03 00:24:07 +0000204 }
wdenk8bde7f72003-06-27 21:31:46 +0000205 else
wdenkc6097192002-11-03 00:24:07 +0000206 {
wdenk8bde7f72003-06-27 21:31:46 +0000207 FPGA_WRITE_0;
wdenkc6097192002-11-03 00:24:07 +0000208 }
wdenk8bde7f72003-06-27 21:31:46 +0000209 fpgadata[i] <<= 1;
210 }
wdenkc6097192002-11-03 00:24:07 +0000211 }
212#else
213 /* send 0xff 0x20 */
214 FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
215 FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
216 FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_1; FPGA_WRITE_0;
217 FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0;
218
219 /*
220 ** Bit_DeCompression
221 ** Code 1 .. maxOnes : n '1's followed by '0'
222 ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
223 ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
224 ** 255 : '1'
225 */
226
227 for (i=index; i<size; i++)
228 {
229 b = fpgadata[i];
230 if ((b >= 1) && (b <= MAX_ONES))
231 {
232 for(bit=0; bit<b; bit++)
wdenk8bde7f72003-06-27 21:31:46 +0000233 {
234 FPGA_WRITE_1;
235 }
wdenkc6097192002-11-03 00:24:07 +0000236 FPGA_WRITE_0;
237 }
238 else if (b == (MAX_ONES+1))
239 {
240 for(bit=1; bit<b; bit++)
wdenk8bde7f72003-06-27 21:31:46 +0000241 {
242 FPGA_WRITE_1;
243 }
wdenkc6097192002-11-03 00:24:07 +0000244 }
245 else if ((b >= (MAX_ONES+2)) && (b <= 254))
246 {
247 for(bit=0; bit<(b-(MAX_ONES+2)); bit++)
wdenk8bde7f72003-06-27 21:31:46 +0000248 {
249 FPGA_WRITE_0;
250 }
251 FPGA_WRITE_1;
wdenkc6097192002-11-03 00:24:07 +0000252 }
253 else if (b == 255)
wdenk8bde7f72003-06-27 21:31:46 +0000254 {
255 FPGA_WRITE_1;
256 }
wdenkc6097192002-11-03 00:24:07 +0000257 }
258#endif
259
stroese0621f6f2004-12-16 18:43:13 +0000260 DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
261 DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
wdenkc6097192002-11-03 00:24:07 +0000262
263 /*
264 * Check if fpga's DONE signal - correctly booted ?
265 */
266
267 /* Wait for FPGA end of programming period . */
268 count = 0;
stroese0621f6f2004-12-16 18:43:13 +0000269 while (!(FPGA_DONE_STATE))
wdenkc6097192002-11-03 00:24:07 +0000270 {
271 udelay(1000); /* wait 1ms */
272 /* Check for timeout */
273 if (count++ > 3)
wdenk8bde7f72003-06-27 21:31:46 +0000274 {
275 DBG("FPGA: Booting failed!\n");
276 return ERROR_FPGA_PRG_DONE;
277 }
wdenkc6097192002-11-03 00:24:07 +0000278 }
279
280 DBG("FPGA: Booting successful!\n");
281 return 0;
282}