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Giulio Benettie12b7372020-01-10 15:47:04 +01001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2019
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
Giulio Benettie12b7372020-01-10 15:47:04 +01007#include "armv7-m.dtsi"
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/imxrt1050-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/memory/imxrt-sdram.h>
12
13/ {
Giulio Benetti22aa2862020-04-08 17:11:05 +020014 #address-cells = <1>;
15 #size-cells = <1>;
16
Giulio Benettie12b7372020-01-10 15:47:04 +010017 aliases {
Giulio Benettibb8af5f2020-04-08 17:10:21 +020018 display0 = &lcdif;
Giulio Benettie12b7372020-01-10 15:47:04 +010019 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 mmc0 = &usdhc1;
25 serial0 = &lpuart1;
26 };
27
28 clocks {
29 u-boot,dm-spl;
30
31 osc {
32 u-boot,dm-spl;
33 compatible = "fsl,imx-osc", "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <24000000>;
36 };
37 };
38
39 soc {
40 u-boot,dm-spl;
41
42 semc: semc@402f0000 {
43 u-boot,dm-spl;
44 compatible = "fsl,imxrt-semc";
45 reg = <0x402f0000 0x4000>;
46 clocks = <&clks IMXRT1050_CLK_SEMC>;
47 pinctrl-0 = <&pinctrl_semc>;
48 pinctrl-names = "default";
49 status = "okay";
50 };
51
52 lpuart1: serial@40184000 {
53 compatible = "fsl,imxrt-lpuart";
54 reg = <0x40184000 0x4000>;
55 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&clks IMXRT1050_CLK_LPUART1>;
57 clock-names = "per";
58 status = "disabled";
59 };
60
61 iomuxc: iomuxc@401f8000 {
62 compatible = "fsl,imxrt-iomuxc";
63 reg = <0x401f8000 0x4000>;
64 fsl,mux_mask = <0x7>;
65 };
66
67 clks: ccm@400fc000 {
68 u-boot,dm-spl;
69 compatible = "fsl,imxrt1050-ccm";
70 reg = <0x400fc000 0x4000>;
71 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
73 #clock-cells = <1>;
74 };
75
76 usdhc1: usdhc@402c0000 {
77 u-boot,dm-spl;
78 compatible = "fsl,imxrt-usdhc";
79 reg = <0x402c0000 0x10000>;
80 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&clks IMXRT1050_CLK_USDHC1>;
82 clock-names = "per";
83 bus-width = <4>;
84 fsl,tuning-start-tap = <20>;
85 fsl,tuning-step= <2>;
86 status = "disabled";
87 };
88
89 gpio1: gpio@401b8000 {
90 u-boot,dm-spl;
91 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
92 reg = <0x401b8000 0x4000>;
93 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
95 gpio-controller;
96 #gpio-cells = <2>;
97 interrupt-controller;
98 #interrupt-cells = <2>;
99 };
100
101 gpio2: gpio@401bc000 {
102 u-boot,dm-spl;
103 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
104 reg = <0x401bc000 0x4000>;
105 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
107 gpio-controller;
108 #gpio-cells = <2>;
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 };
112
113 gpio3: gpio@401c0000 {
114 u-boot,dm-spl;
115 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
116 reg = <0x401c0000 0x4000>;
117 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
119 gpio-controller;
120 #gpio-cells = <2>;
121 interrupt-controller;
122 #interrupt-cells = <2>;
123 };
124
125 gpio4: gpio@401c4000 {
126 u-boot,dm-spl;
127 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
128 reg = <0x401c4000 0x4000>;
129 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
131 gpio-controller;
132 #gpio-cells = <2>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
135 };
136
137 gpio5: gpio@400c0000 {
138 u-boot,dm-spl;
139 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
140 reg = <0x400c0000 0x4000>;
141 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
143 gpio-controller;
144 #gpio-cells = <2>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
147 };
Giulio Benettibb8af5f2020-04-08 17:10:21 +0200148
149 lcdif: lcdif@402b8000 {
150 compatible = "fsl,imxrt-lcdif";
151 reg = <0x402b8000 0x10000>;
152 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&clks IMXRT1050_CLK_LCDIF>;
154 clock-names = "per";
155 status = "disabled";
156 };
Giulio Benettie12b7372020-01-10 15:47:04 +0100157 };
158};