| Dinh Nguyen | 84b124d | 2019-04-23 16:55:03 -0500 | [diff] [blame] | 1 | # |
| 2 | # Cache controllers |
| 3 | # |
| 4 | |
| 5 | menu "Cache Controller drivers" |
| 6 | |
| 7 | config CACHE |
| 8 | bool "Enable Driver Model for Cache controllers" |
| 9 | depends on DM |
| 10 | help |
| 11 | Enable driver model for cache controllers that are found on |
| 12 | most CPU's. Cache is memory that the CPU can access directly and |
| 13 | is usually located on the same chip. This uclass can be used for |
| 14 | configuring settings that be found from a device tree file. |
| 15 | |
| Dinh Nguyen | 88ebf58 | 2019-04-23 16:55:04 -0500 | [diff] [blame] | 16 | config L2X0_CACHE |
| 17 | tristate "PL310 cache driver" |
| 18 | select CACHE |
| 19 | depends on ARM |
| 20 | help |
| 21 | This driver is for the PL310 cache controller commonly found on |
| 22 | ARMv7(32-bit) devices. The driver configures the cache settings |
| 23 | found in the device tree. |
| 24 | |
| Rick Chen | 4fa4267 | 2019-08-28 18:46:06 +0800 | [diff] [blame] | 25 | config V5L2_CACHE |
| 26 | bool "Andes V5L2 cache driver" |
| 27 | select CACHE |
| 28 | depends on RISCV_NDS_CACHE |
| 29 | help |
| 30 | Support Andes V5L2 cache controller in AE350 platform. |
| 31 | It will configure tag and data ram timing control from the |
| 32 | device tree and enable L2 cache. |
| 33 | |
| Ley Foon Tan | fec7ddc | 2019-11-27 15:55:24 +0800 | [diff] [blame] | 34 | config NCORE_CACHE |
| 35 | bool "Arteris Ncore cache coherent unit driver" |
| 36 | select CACHE |
| 37 | help |
| 38 | This driver is for the Arteris Ncore cache coherent unit (CCU) |
| 39 | controller. The driver initializes cache directories and coherent |
| 40 | agent interfaces. |
| 41 | |
| Dinh Nguyen | 84b124d | 2019-04-23 16:55:03 -0500 | [diff] [blame] | 42 | endmenu |