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John Otkend4024bb2007-07-26 17:49:11 +02001/*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2005-2007
6 * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30
31#define CONFIG_405EP 1 /* this is a PPC405 CPU */
32#define CONFIG_4xx 1 /* member of PPC4xx family */
33#define CONFIG_TAIHU 1 /* on a taihu board */
34
Wolfgang Denk2ae18242010-10-06 09:05:45 +020035#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
36
Stefan Roese72675dc2008-06-06 15:55:21 +020037/*
38 * Include common defines/options for all AMCC eval boards
39 */
40#define CONFIG_HOSTNAME taihu
41#include "amcc-common.h"
42
John Otkend4024bb2007-07-26 17:49:11 +020043#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
44
45#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
46
47#define CONFIG_NO_SERIAL_EEPROM
48
49/*----------------------------------------------------------------------------*/
50#ifdef CONFIG_NO_SERIAL_EEPROM
51
52/*
53!-------------------------------------------------------------------------------
54! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
55! assuming a 33MHz input clock to the 405EP from the C9531.
56!-------------------------------------------------------------------------------
57*/
58#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
59 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
60 PLL_MALDIV_1 | PLL_PCIDIV_3)
61#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
62 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
63 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
64#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
65 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
66 PLL_MALDIV_1 | PLL_PCIDIV_1)
67#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
68 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
69 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
70
71#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
72#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
73#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
74#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
75
76#endif
77/*----------------------------------------------------------------------------*/
78
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020079#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
John Otkend4024bb2007-07-26 17:49:11 +020080
Stefan Roese72675dc2008-06-06 15:55:21 +020081/*
82 * Default environment variables
83 */
84#define CONFIG_EXTRA_ENV_SETTINGS \
85 CONFIG_AMCC_DEF_ENV \
86 CONFIG_AMCC_DEF_ENV_PPC \
87 CONFIG_AMCC_DEF_ENV_NOR_UPD \
John Otkend4024bb2007-07-26 17:49:11 +020088 "kernel_addr=FC000000\0" \
89 "ramdisk_addr=FC180000\0" \
John Otkend4024bb2007-07-26 17:49:11 +020090 ""
John Otkend4024bb2007-07-26 17:49:11 +020091
John Otkend4024bb2007-07-26 17:49:11 +020092#define CONFIG_PHY_ADDR 0x14 /* PHY address */
Stefan Roesea00eccf2008-05-08 11:05:15 +020093#define CONFIG_HAS_ETH0
John Otkend4024bb2007-07-26 17:49:11 +020094#define CONFIG_HAS_ETH1
95#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
John Otkend4024bb2007-07-26 17:49:11 +020096#define CONFIG_PHY_RESET 1
97
Stefan Roese3b3bff42007-08-14 16:36:29 +020098/*
Stefan Roese72675dc2008-06-06 15:55:21 +020099 * Commands additional to the ones defined in amcc-common.h
Stefan Roese3b3bff42007-08-14 16:36:29 +0200100 */
Stefan Roese3b3bff42007-08-14 16:36:29 +0200101#define CONFIG_CMD_CACHE
Stefan Roese3b3bff42007-08-14 16:36:29 +0200102#define CONFIG_CMD_PCI
Stefan Roese3b3bff42007-08-14 16:36:29 +0200103#define CONFIG_CMD_SDRAM
104#define CONFIG_CMD_SPI
John Otkend4024bb2007-07-26 17:49:11 +0200105
John Otkend4024bb2007-07-26 17:49:11 +0200106#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
108#define CONFIG_SYS_SDRAM_BANKS 2
John Otkend4024bb2007-07-26 17:49:11 +0200109
110/*
111 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
112 */
113#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
114#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
115
116/* SDRAM timings used in datasheet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
118#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
119#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
120#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
121#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
John Otkend4024bb2007-07-26 17:49:11 +0200122
123/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
125 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
126 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
John Otkend4024bb2007-07-26 17:49:11 +0200127 * The Linux BASE_BAUD define should match this configuration.
128 * baseBaud = cpuClock/(uartDivisor*16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
John Otkend4024bb2007-07-26 17:49:11 +0200130 * set Linux BASE_BAUD to 403200.
131 */
Stefan Roese550650d2010-09-20 16:05:31 +0200132#define CONFIG_CONS_INDEX 2 /* Use UART1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
134#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
135#define CONFIG_SYS_BASE_BAUD 691200
John Otkend4024bb2007-07-26 17:49:11 +0200136
John Otkend4024bb2007-07-26 17:49:11 +0200137/*-----------------------------------------------------------------------
138 * I2C stuff
139 *-----------------------------------------------------------------------
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
John Otkend4024bb2007-07-26 17:49:11 +0200142
Peter Tyser0f89c542009-04-18 22:34:03 -0500143#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid i2c probe hangup (why?) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
John Otkend4024bb2007-07-26 17:49:11 +0200145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
147#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
John Otkend4024bb2007-07-26 17:49:11 +0200148
149#define CONFIG_SOFT_SPI
150#define SPI_SCL spi_scl
151#define SPI_SDA spi_sda
152#define SPI_READ spi_read()
153#define SPI_DELAY udelay(2)
154#ifndef __ASSEMBLY__
155void spi_scl(int);
156void spi_sda(int);
157unsigned char spi_read(void);
158#endif
159
160/* standard dtt sensor configuration */
161#define CONFIG_DTT_DS1775 1
162#define CONFIG_DTT_SENSORS { 0 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_I2C_DTT_ADDR 0x49
John Otkend4024bb2007-07-26 17:49:11 +0200164
165/*-----------------------------------------------------------------------
166 * PCI stuff
167 *-----------------------------------------------------------------------
168 */
169#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
170#define PCI_HOST_FORCE 1 /* configure as pci host */
171#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
172
173#define CONFIG_PCI /* include pci support */
174#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
175#define CONFIG_PCI_PNP /* do pci plug-and-play */
176 /* resource configuration */
177#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
180#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
181#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
182#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
183#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
184#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
185#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
186#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
187#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
John Otkend4024bb2007-07-26 17:49:11 +0200188#define CONFIG_EEPRO100 1
189
190/*-----------------------------------------------------------------------
191 * Start addresses for the final memory configuration
192 * (Set up by the startup code)
John Otkend4024bb2007-07-26 17:49:11 +0200193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_BASE 0xFFE00000
John Otkend4024bb2007-07-26 17:49:11 +0200195
196/*-----------------------------------------------------------------------
197 * FLASH organization
198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
200#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
John Otkend4024bb2007-07-26 17:49:11 +0200201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
203#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
John Otkend4024bb2007-07-26 17:49:11 +0200204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_FLASH_ADDR0 0x555
206#define CONFIG_SYS_FLASH_ADDR1 0x2aa
207#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
John Otkend4024bb2007-07-26 17:49:11 +0200208
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200209#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200210#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
John Otkend4024bb2007-07-26 17:49:11 +0200213
214/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200215#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
216#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200217#endif /* CONFIG_ENV_IS_IN_FLASH */
John Otkend4024bb2007-07-26 17:49:11 +0200218
219/*-----------------------------------------------------------------------
220 * NVRAM organization
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
223#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
John Otkend4024bb2007-07-26 17:49:11 +0200224
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200225#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200226#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
227#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env*/
John Otkend4024bb2007-07-26 17:49:11 +0200229#endif
230
231/*-----------------------------------------------------------------------
232 * PPC405 GPIO Configuration
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
John Otkend4024bb2007-07-26 17:49:11 +0200235{ \
236/* GPIO Core 0 */ \
237{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
238{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
239{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
240{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
241{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
242{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
243{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
244{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
245{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
246{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
247{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
248{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
249{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
250{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
251{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
252{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
253{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
254{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
255{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
256{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
257{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
258{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
259{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
260{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
261{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
262{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
263{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
264{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200265{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
John Otkend4024bb2007-07-26 17:49:11 +0200266{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
267{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
268{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
269} \
270}
271
John Otkend4024bb2007-07-26 17:49:11 +0200272/*
273 * Init Memory Controller:
274 *
275 * BR0/1 and OR0/1 (FLASH)
276 */
277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
John Otkend4024bb2007-07-26 17:49:11 +0200279#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
280
281/*-----------------------------------------------------------------------
282 * Definitions for initial stack pointer and data area (in data cache)
283 */
284/* use on chip memory (OCM) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_TEMP_STACK_OCM 1
John Otkend4024bb2007-07-26 17:49:11 +0200286
287/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
289#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
290#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200291#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
John Otkend4024bb2007-07-26 17:49:11 +0200292
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200293#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
John Otkend4024bb2007-07-26 17:49:11 +0200295
296/*-----------------------------------------------------------------------
297 * External Bus Controller (EBC) Setup
298 */
299
300/* Memory Bank 0 (Flash/SRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_EBC_PB0AP 0x03815600
302#define CONFIG_SYS_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
John Otkend4024bb2007-07-26 17:49:11 +0200303
304/* Memory Bank 1 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_EBC_PB1AP 0x05815600
306#define CONFIG_SYS_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
John Otkend4024bb2007-07-26 17:49:11 +0200307
308/* Memory Bank 2 (USB device) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_EBC_PB2AP 0x03016600
310#define CONFIG_SYS_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
John Otkend4024bb2007-07-26 17:49:11 +0200311
312/* Memory Bank 3 (LCM and D-flip-flop) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_EBC_PB3AP 0x158FF600
314#define CONFIG_SYS_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
John Otkend4024bb2007-07-26 17:49:11 +0200315
316/* Memory Bank 4 (not install) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_EBC_PB4AP 0x158FF600
318#define CONFIG_SYS_EBC_PB4CR 0x5021A000
John Otkend4024bb2007-07-26 17:49:11 +0200319
John Otkend4024bb2007-07-26 17:49:11 +0200320#define CPLD_REG0_ADDR 0x50100000
321#define CPLD_REG1_ADDR 0x50100001
Stefan Roesea00eccf2008-05-08 11:05:15 +0200322
John Otkend4024bb2007-07-26 17:49:11 +0200323#endif /* __CONFIG_H */