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Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +00001/*
2 * Board functions for IGEP COM AQUILA/CYGNUS based boards
3 *
4 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +00007 */
8
9#include <common.h>
10#include <errno.h>
11#include <spl.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/hardware.h>
14#include <asm/arch/omap.h>
15#include <asm/arch/ddr_defs.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/gpio.h>
18#include <asm/arch/mmc_host_def.h>
19#include <asm/arch/sys_proto.h>
20#include <asm/io.h>
21#include <asm/emif.h>
22#include <asm/gpio.h>
23#include <i2c.h>
24#include <miiphy.h>
25#include <cpsw.h>
26#include "board.h"
27
28DECLARE_GLOBAL_DATA_PTR;
29
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000030/* MII mode defines */
31#define RMII_MODE_ENABLE 0x4D
32
33static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
34
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000035#ifdef CONFIG_SPL_BUILD
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000036static const struct ddr_data ddr3_data = {
37 .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
38 .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
39 .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
40 .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
41 .datadldiff0 = PHY_DLL_LOCK_DIFF,
42};
43
44static const struct cmd_control ddr3_cmd_ctrl_data = {
45 .cmd0csratio = K4B2G1646EBIH9_RATIO,
46 .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
47 .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
48
49 .cmd1csratio = K4B2G1646EBIH9_RATIO,
50 .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
51 .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
52
53 .cmd2csratio = K4B2G1646EBIH9_RATIO,
54 .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
55 .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
56};
57
58static struct emif_regs ddr3_emif_reg_data = {
59 .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
60 .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
61 .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
62 .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
63 .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
64 .zq_config = K4B2G1646EBIH9_ZQ_CFG,
65 .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
66};
Lokesh Vutla94d77fb2013-07-30 10:48:52 +053067
68#define OSC (V_OSCK/1000000)
69const struct dpll_params dpll_ddr = {
70 303, OSC-1, 1, -1, -1, -1, -1};
71
72const struct dpll_params *get_dpll_ddr_params(void)
73{
74 return &dpll_ddr;
75}
76
Heiko Schocher06604812013-07-30 10:48:54 +053077void set_uart_mux_conf(void)
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000078{
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000079 enable_uart0_pin_mux();
Heiko Schocher06604812013-07-30 10:48:54 +053080}
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000081
Heiko Schocher06604812013-07-30 10:48:54 +053082void set_mux_conf_regs(void)
83{
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000084 enable_board_pin_mux();
Heiko Schocher06604812013-07-30 10:48:54 +053085}
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000086
Heiko Schocher06604812013-07-30 10:48:54 +053087void sdram_init(void)
88{
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000089 config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
90 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000091}
Heiko Schocher06604812013-07-30 10:48:54 +053092#endif
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000093
94/*
95 * Basic board specific setup. Pinmux has been handled already.
96 */
97int board_init(void)
98{
99 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
100
101 gpmc_init();
102
103 return 0;
104}
105
106#if defined(CONFIG_DRIVER_TI_CPSW)
107static void cpsw_control(int enabled)
108{
109 /* VTP can be added here */
110
111 return;
112}
113
114static struct cpsw_slave_data cpsw_slaves[] = {
115 {
116 .slave_reg_ofs = 0x208,
117 .sliver_reg_ofs = 0xd80,
118 .phy_id = 0,
119 .phy_if = PHY_INTERFACE_MODE_RMII,
120 },
121};
122
123static struct cpsw_platform_data cpsw_data = {
124 .mdio_base = CPSW_MDIO_BASE,
125 .cpsw_base = CPSW_BASE,
126 .mdio_div = 0xff,
127 .channels = 8,
128 .cpdma_reg_ofs = 0x800,
129 .slaves = 1,
130 .slave_data = cpsw_slaves,
131 .ale_reg_ofs = 0xd00,
132 .ale_entries = 1024,
133 .host_port_reg_ofs = 0x108,
134 .hw_stats_reg_ofs = 0x900,
135 .mac_control = (1 << 5),
136 .control = cpsw_control,
137 .host_port_num = 0,
138 .version = CPSW_CTRL_VERSION_2,
139};
140
141int board_eth_init(bd_t *bis)
142{
143 int rv, ret = 0;
144 uint8_t mac_addr[6];
145 uint32_t mac_hi, mac_lo;
146
147 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
148 /* try reading mac address from efuse */
149 mac_lo = readl(&cdev->macid0l);
150 mac_hi = readl(&cdev->macid0h);
151 mac_addr[0] = mac_hi & 0xFF;
152 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
153 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
154 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
155 mac_addr[4] = mac_lo & 0xFF;
156 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
157 if (is_valid_ether_addr(mac_addr))
158 eth_setenv_enetaddr("ethaddr", mac_addr);
159 }
160
161 writel(RMII_MODE_ENABLE, &cdev->miisel);
162
163 rv = cpsw_register(&cpsw_data);
164 if (rv < 0)
165 printf("Error %d registering CPSW switch\n", rv);
166 else
167 ret += rv;
168
169 return ret;
170}
171#endif
172