blob: 7e6d239d13d207c334da837485fc906ecf4ac792 [file] [log] [blame]
Simon Glass8ef07572014-11-12 22:42:07 -07001/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2008
4 * Graeme Russ, graeme.russ@gmail.com.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#include <configs/x86-common.h>
17
Bin Meng24ef0422015-01-06 22:14:19 +080018
Simon Glass8ef07572014-11-12 22:42:07 -070019#define CONFIG_SYS_MONITOR_LEN (1 << 20)
Bin Meng24ef0422015-01-06 22:14:19 +080020
Simon Glass65dd74a2014-11-12 22:42:28 -070021#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
Simon Glass437c2b72014-11-12 22:42:25 -070022#define CONFIG_BOARD_EARLY_INIT_F
Simon Glass8ef07572014-11-12 22:42:07 -070023
Simon Glass8ef07572014-11-12 22:42:07 -070024#define CONFIG_NR_DRAM_BANKS 8
Bin Meng8c5224c2014-12-17 15:50:42 +080025#define CONFIG_X86_MRC_ADDR 0xfffa0000
Simon Glass65dd74a2014-11-12 22:42:28 -070026#define CONFIG_CACHE_MRC_SIZE_KB 512
Simon Glass8ef07572014-11-12 22:42:07 -070027
Bin Meng41702ba2014-12-17 15:50:47 +080028#define CONFIG_X86_SERIAL
Simon Glass8ef07572014-11-12 22:42:07 -070029
30#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
31 PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
32 {PCI_VENDOR_ID_INTEL, \
33 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
34 {PCI_VENDOR_ID_INTEL, \
35 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
36 {PCI_VENDOR_ID_INTEL, \
37 PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
38
Bin Meng63faf252014-12-17 15:50:43 +080039#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin
Simon Glass62d0c5e2014-11-14 20:56:38 -070040#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
Simon Glass8ef07572014-11-12 22:42:07 -070041
Simon Glass6e5b12b2014-11-12 22:42:13 -070042#define CONFIG_PCI_MEM_BUS 0xe0000000
43#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
44#define CONFIG_PCI_MEM_SIZE 0x10000000
45
46#define CONFIG_PCI_PREF_BUS 0xd0000000
47#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
48#define CONFIG_PCI_PREF_SIZE 0x10000000
49
50#define CONFIG_PCI_IO_BUS 0x1000
51#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
52#define CONFIG_PCI_IO_SIZE 0xefff
53
Simon Glassb6b4a0e2014-11-14 18:18:29 -070054#define CONFIG_SYS_EARLY_PCI_INIT
55#define CONFIG_PCI_PNP
56
Simon Glassa6fa83f2014-11-14 20:56:44 -070057#define CONFIG_BIOSEMU
58#define VIDEO_IO_OFFSET 0
59#define CONFIG_X86EMU_RAW_IO
60
Simon Glass22e131c2014-11-14 20:56:45 -070061#define CONFIG_CROS_EC
62#define CONFIG_CROS_EC_LPC
63#define CONFIG_CMD_CROS_EC
64#define CONFIG_ARCH_EARLY_INIT_R
65
Simon Glass8ef07572014-11-12 22:42:07 -070066#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
67 "stdout=vga,serial\0" \
68 "stderr=vga,serial\0"
69
70#endif /* __CONFIG_H */