blob: 8caeca64307c233bcb509bd12d3a78859140b28a [file] [log] [blame]
Simon Glass8ef07572014-11-12 22:42:07 -07001/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2008
4 * Graeme Russ, graeme.russ@gmail.com.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#include <configs/x86-common.h>
17
18#define CONFIG_SYS_CAR_ADDR 0xff7e0000
19#define CONFIG_SYS_CAR_SIZE (128 * 1024)
20#define CONFIG_SYS_MONITOR_LEN (1 << 20)
Simon Glass65dd74a2014-11-12 22:42:28 -070021#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
Simon Glassfce7b272014-11-12 22:42:08 -070022#define CONFIG_SYS_X86_START16 0xfffff800
Simon Glass437c2b72014-11-12 22:42:25 -070023#define CONFIG_BOARD_EARLY_INIT_F
Simon Glass8ef07572014-11-12 22:42:07 -070024#define CONFIG_BOARD_EARLY_INIT_R
Simon Glass65dd74a2014-11-12 22:42:28 -070025#define CONFIG_DISPLAY_CPUINFO
Simon Glass8ef07572014-11-12 22:42:07 -070026
Simon Glassfce7b272014-11-12 22:42:08 -070027#define CONFIG_X86_RESET_VECTOR
Simon Glass8ef07572014-11-12 22:42:07 -070028#define CONFIG_NR_DRAM_BANKS 8
Simon Glass65dd74a2014-11-12 22:42:28 -070029#define CONFIG_X86_MRC_START 0xfffa0000
30#define CONFIG_CACHE_MRC_SIZE_KB 512
Simon Glass8ef07572014-11-12 22:42:07 -070031
32#define CONFIG_COREBOOT_SERIAL
33
34#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
35 PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
36 {PCI_VENDOR_ID_INTEL, \
37 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
38 {PCI_VENDOR_ID_INTEL, \
39 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
40 {PCI_VENDOR_ID_INTEL, \
41 PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
42
43/*
44 * These common x86 features are not yet supported, but are added in
45 * follow-on patches in this series. Add undefs here to avoid every patch
46 * having to put things back into x86-common.h
47 */
Simon Glass8ef07572014-11-12 22:42:07 -070048#undef CONFIG_VIDEO
49#undef CONFIG_CFB_CONSOLE
Simon Glass8ef07572014-11-12 22:42:07 -070050#undef CONFIG_ICH_SPI
51#undef CONFIG_SPI
52#undef CONFIG_CMD_SPI
53#undef CONFIG_CMD_SF
54#undef CONFIG_USB_EHCI
55#undef CONFIG_CMD_USB
56#undef CONFIG_CMD_SCSI
57
Simon Glass6e5b12b2014-11-12 22:42:13 -070058#define CONFIG_PCI_MEM_BUS 0xe0000000
59#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
60#define CONFIG_PCI_MEM_SIZE 0x10000000
61
62#define CONFIG_PCI_PREF_BUS 0xd0000000
63#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
64#define CONFIG_PCI_PREF_SIZE 0x10000000
65
66#define CONFIG_PCI_IO_BUS 0x1000
67#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
68#define CONFIG_PCI_IO_SIZE 0xefff
69
Simon Glass8ef07572014-11-12 22:42:07 -070070#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
71 "stdout=vga,serial\0" \
72 "stderr=vga,serial\0"
73
74#endif /* __CONFIG_H */