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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 071d897c96460c414786ef1d40f3e56f8d9fb8cb / . / include / configs / FADS860T.h
blob: 2c9438988ed4f846080a7a8233fe9b7b2c4d7c5e [file] [log] [blame]
wdenka9ab73b2002-10-11 15:28:05 +0000[diff] [blame]1/*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
6 *
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
8 */
9
10/*
11 * 1999-nov-26: The FADS is using the following physical memorymap:
12 *
13 * ff020000 -> ff02ffff : pcmcia
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom
17 * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
18 */
19
20/* ------------------------------------------------------------------------- */
21
22/*
23 * board/config.h - configuration options, board specific
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
33#include <mpc8xx_irq.h>
34
35#define CONFIG_MPC860 1
36#define CONFIG_MPC860T 1
37#define CONFIG_FADS 1
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42#define CONFIG_BAUDRATE 9600
43#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
44
45#if 0
46#define MPC8XX_FACT 10 /* Multiply by 10 */
47#define MPC8XX_XIN 5000000 /* 5 MHz in */
48#else
49#define MPC8XX_FACT 12 /* Multiply by 12 */
50#define MPC8XX_XIN 4000000 /* 4 MHz in */
51#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
52#endif
53
54#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
55
56#if 1
57#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
58#else
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60#endif
61
62#define CONFIG_BOOTCOMMAND "bootm 2800100" /* autoboot command */
63#define CONFIG_BOOTARGS ""
64
65#undef CONFIG_WATCHDOG /* watchdog disabled */
66
67/* ATA / IDE and partition support */
68#define CONFIG_MAC_PARTITION 1
69#define CONFIG_DOS_PARTITION 1
70#define CONFIG_ISO_PARTITION 1
71#undef CONFIG_ATAPI
72#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
73#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
74#undef CONFIG_IDE_LED /* LED for ide not supported */
75#undef CONFIG_IDE_RESET /* reset for ide not supported */
76
77/* choose SCC1 ethernet (10BASET on motherboard)
78 * or FEC ethernet (10/100 on daughterboard)
79 */
80#if 1
81#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
82#undef CONFIG_FEC_ENET /* disable FEC ethernet */
83#else
84#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
85#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
86#define CFG_DISCOVER_PHY
87#endif
88#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
89#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
90#endif
91
92/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
93#include <cmd_confdefs.h>
94
95/*
96 * Miscellaneous configurable options
97 */
98#undef CFG_LONGHELP /* undef to save memory */
99#define CFG_PROMPT "=>" /* Monitor Command Prompt */
100#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
101#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
102#else
103#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
104#endif
105#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
106#define CFG_MAXARGS 16 /* max number of command args */
107#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
108
109#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
110#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
111
112#define CFG_LOAD_ADDR 0x00100000
113
114#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
115
116#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
117
118/*
119 * Low Level Configuration Settings
120 * (address mappings, register initial values, etc.)
121 * You should know what you are doing if you make changes here.
122 */
123/*-----------------------------------------------------------------------
124 * Internal Memory Mapped Register
125 */
126#define CFG_IMMR 0xFF000000
127#define CFG_IMMR_SIZE ((uint)(64 * 1024))
128
129/*-----------------------------------------------------------------------
130 * Definitions for initial stack pointer and data area (in DPRAM)
131 */
132#define CFG_INIT_RAM_ADDR CFG_IMMR
133#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
134#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
135#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
136#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
137
138/*-----------------------------------------------------------------------
139 * Start addresses for the final memory configuration
140 * (Set up by the startup code)
141 * Please note that CFG_SDRAM_BASE _must_ start at 0
142 */
143#define CFG_SDRAM_BASE 0x00000000
144
145#define CFG_FLASH_BASE 0x02800000
146
147#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
148
149#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */
150#define CFG_MONITOR_BASE CFG_FLASH_BASE
151#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
152
153/*
154 * For booting Linux, the board info and command line data
155 * have to be in the first 8 MB of memory, since this is
156 * the maximum mapped by the Linux kernel during initialization.
157 */
158#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
159/*-----------------------------------------------------------------------
160 * FLASH organization
161 */
wdenk5d232d02003-05-22 22:52:13 +0000[diff] [blame]162#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
163#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
wdenka9ab73b2002-10-11 15:28:05 +0000[diff] [blame]164
165#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
166#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
167
168#define CFG_ENV_IS_IN_FLASH 1
169#define CFG_ENV_OFFSET 0x00040000
170#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
171
172#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
173
174/*-----------------------------------------------------------------------
175 * Cache Configuration
176 */
177#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
178#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
179#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
180#endif
181
182/*-----------------------------------------------------------------------
183 * SYPCR - System Protection Control 11-9
184 * SYPCR can only be written once after reset!
185 *-----------------------------------------------------------------------
186 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
187 */
188#if defined(CONFIG_WATCHDOG)
189#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
190 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
191#else
192#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
193#endif
194
195/*-----------------------------------------------------------------------
196 * SIUMCR - SIU Module Configuration 11-6
197 *-----------------------------------------------------------------------
198 * PCMCIA config., multi-function pin tri-state
199 */
200#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
201
202/*-----------------------------------------------------------------------
203 * TBSCR - Time Base Status and Control 11-26
204 *-----------------------------------------------------------------------
205 * Clear Reference Interrupt Status, Timebase freezing enabled
206 */
207#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
208
209/*-----------------------------------------------------------------------
210 * PISCR - Periodic Interrupt Status and Control 11-31
211 *-----------------------------------------------------------------------
212 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
213 */
214#define CFG_PISCR (PISCR_PS | PISCR_PITF)
215
216/*-----------------------------------------------------------------------
217 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
218 *-----------------------------------------------------------------------
219 * set the PLL, the low-power modes and the reset control (15-29)
220 */
221#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
222 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
223
224/*-----------------------------------------------------------------------
225 * SCCR - System Clock and reset Control Register 15-27
226 *-----------------------------------------------------------------------
227 * Set clock output, timebase and RTC source and divider,
228 * power management and some other internal clocks
229 */
230#define SCCR_MASK SCCR_EBDF11
231#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
232
233 /*-----------------------------------------------------------------------
234 *
235 *-----------------------------------------------------------------------
236 *
237 */
238#define CFG_DER 0
239
240/* Because of the way the 860 starts up and assigns CS0 the
241* entire address space, we have to set the memory controller
242* differently. Normally, you write the option register
243* first, and then enable the chip select by writing the
244* base register. For CS0, you must write the base register
245* first, followed by the option register.
246*/
247
248/*
249 * Init Memory Controller:
250 *
251 * BR0/1 and OR0/1 (FLASH)
252 */
253/* the other CS:s are determined by looking at parameters in BCSRx */
254
255#define BCSR_ADDR ((uint) 0xFF010000)
256#define BCSR_SIZE ((uint)(64 * 1024))
257
258#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
259#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
260
261/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
262#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
263
264#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
265
266#ifdef USE_REAL_FLASH_VALUES
267/*
268 * These values fit our FADS860T ...
269 * The "default" behaviour with 1Mbyte initial doesn't work for us!
270 */
271#define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */
272#define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */
273#else
274#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
275#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
276#endif
277
278/* BCSRx - Board Control and Status Registers */
279#define CFG_OR1_REMAP CFG_OR0_REMAP
280#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
281#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
282
283
284/*
285 * Memory Periodic Timer Prescaler
286 */
287
288/* periodic timer for refresh */
289#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
290
291/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
292#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
293#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
294
295/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
296#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
297#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
298
299/*
300 * MAMR settings for SDRAM
301 */
302
303/* 8 column SDRAM */
304#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
305 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
306 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
307/* 9 column SDRAM */
308#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
309 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
310 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
311
312#define CFG_MAMR 0x13a01114
313/*
314 * Internal Definitions
315 *
316 * Boot Flags
317 */
318#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
319#define BOOTFLAG_WARM 0x02 /* Software reboot */
320
321
322/* values according to the manual */
323
324
325#define PCMCIA_MEM_ADDR ((uint)0xff020000)
326#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
327
328#define BCSR0 ((uint) (BCSR_ADDR + 00))
329#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
330#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
331#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
332#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
333
334/* FADS bitvalues by Helmut Buchsbaum
335 * see MPC8xxADS User's Manual for a proper description
336 * of the following structures
337 */
338
339#define BCSR0_ERB ((uint)0x80000000)
340#define BCSR0_IP ((uint)0x40000000)
341#define BCSR0_BDIS ((uint)0x10000000)
342#define BCSR0_BPS_MASK ((uint)0x0C000000)
343#define BCSR0_ISB_MASK ((uint)0x01800000)
344#define BCSR0_DBGC_MASK ((uint)0x00600000)
345#define BCSR0_DBPC_MASK ((uint)0x00180000)
346#define BCSR0_EBDF_MASK ((uint)0x00060000)
347
348#define BCSR1_FLASH_EN ((uint)0x80000000)
349#define BCSR1_DRAM_EN ((uint)0x40000000)
350#define BCSR1_ETHEN ((uint)0x20000000)
351#define BCSR1_IRDEN ((uint)0x10000000)
352#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
353#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
354#define BCSR1_BCSR_EN ((uint)0x02000000)
355#define BCSR1_RS232EN_1 ((uint)0x01000000)
356#define BCSR1_PCCEN ((uint)0x00800000)
357#define BCSR1_PCCVCC0 ((uint)0x00400000)
358#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
359#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
360#define BCSR1_RS232EN_2 ((uint)0x00040000)
361#define BCSR1_SDRAM_EN ((uint)0x00020000)
362#define BCSR1_PCCVCC1 ((uint)0x00010000)
363
364#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
365#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
366#define BCSR2_DRAM_PD_SHIFT (23)
367#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
368#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
369
370#define BCSR3_DBID_MASK ((ushort)0x3800)
371#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
372#define BCSR3_BREVNR0 ((ushort)0x0080)
373#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
374#define BCSR3_BREVN1 ((ushort)0x0008)
375#define BCSR3_BREVN2_MASK ((ushort)0x0003)
376
377#define BCSR4_ETHLOOP ((uint)0x80000000)
378#define BCSR4_TFPLDL ((uint)0x40000000)
379#define BCSR4_TPSQEL ((uint)0x20000000)
380#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
381#ifdef CONFIG_MPC823
382#define BCSR4_USB_EN ((uint)0x08000000)
383#endif /* CONFIG_MPC823 */
384#ifdef CONFIG_MPC860SAR
385#define BCSR4_UTOPIA_EN ((uint)0x08000000)
386#endif /* CONFIG_MPC860SAR */
387#ifdef CONFIG_MPC860T
388#define BCSR4_FETH_EN ((uint)0x08000000)
389#endif /* CONFIG_MPC860T */
390#ifdef CONFIG_MPC823
391#define BCSR4_USB_SPEED ((uint)0x04000000)
392#endif /* CONFIG_MPC823 */
393#ifdef CONFIG_MPC860T
394#define BCSR4_FETHCFG0 ((uint)0x04000000)
395#endif /* CONFIG_MPC860T */
396#ifdef CONFIG_MPC823
397#define BCSR4_VCCO ((uint)0x02000000)
398#endif /* CONFIG_MPC823 */
399#ifdef CONFIG_MPC860T
400#define BCSR4_FETHFDE ((uint)0x02000000)
401#endif /* CONFIG_MPC860T */
402#ifdef CONFIG_MPC823
403#define BCSR4_VIDEO_ON ((uint)0x00800000)
404#endif /* CONFIG_MPC823 */
405#ifdef CONFIG_MPC823
406#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
407#endif /* CONFIG_MPC823 */
408#ifdef CONFIG_MPC860T
409#define BCSR4_FETHCFG1 ((uint)0x00400000)
410#endif /* CONFIG_MPC860T */
411#ifdef CONFIG_MPC823
412#define BCSR4_VIDEO_RST ((uint)0x00200000)
413#endif /* CONFIG_MPC823 */
414#ifdef CONFIG_MPC860T
415#define BCSR4_FETHRST ((uint)0x00200000)
416#endif /* CONFIG_MPC860T */
417#ifdef CONFIG_MPC823
418#define BCSR4_MODEM_EN ((uint)0x00100000)
419#endif /* CONFIG_MPC823 */
420#ifdef CONFIG_MPC823
421#define BCSR4_DATA_VOICE ((uint)0x00080000)
422#endif /* CONFIG_MPC823 */
423#ifdef CONFIG_MPC850
424#define BCSR4_DATA_VOICE ((uint)0x00080000)
425#endif /* CONFIG_MPC850 */
426
427#define CONFIG_DRAM_50MHZ 1
428#define CONFIG_SDRAM_50MHZ
429
430#ifdef CONFIG_MPC860T
431
432/* Interrupt level assignments.
433*/
434#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
435
436#endif /* CONFIG_MPC860T */
437
438/* We don't use the 8259.
439*/
440#define NR_8259_INTS 0
441
442/* Machine type
443*/
444#define _MACH_8xx (_MACH_fads)
445
446#define CONFIG_DISK_SPINUP_TIME 1000000
447
448
449/* PCMCIA configuration */
450
451#define PCMCIA_MAX_SLOTS 2
452
453#ifdef CONFIG_MPC860
454#define PCMCIA_SLOT_A 1
455#endif
456/*#define CFG_PCMCIA_MEM_SIZE ( 64 << 20) */
457#define CFG_PCMCIA_MEM_ADDR (0x50000000)
458#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
459#define CFG_PCMCIA_DMA_ADDR (0x54000000)
460#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
461#define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
462#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
463#define CFG_PCMCIA_IO_ADDR (0x5C000000)
464#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
465/* we have 8 windows, we take everything up to 60000000 */
466
467#define CFG_ATA_IDE0_OFFSET 0x0000
468
469#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
470
471/* Offset for data I/O */
472#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
473/* Offset for normal register accesses */
474#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
475/* Offset for alternate registers */
476#define CFG_ATA_ALT_OFFSET 0x0000
477/*#define CFG_ATA_ALT_OFFSET 0x0100 */
478
479
480#endif /* __CONFIG_H */