blob: 463a81be20e45b4ec2448c720f39a1f6e0bed74b [file] [log] [blame]
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * (C) Copyright 2006
9 * MicroSys GmbH
10 *
11 * (C) Copyright 2009
12 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33#include <common.h>
34#include <mpc5xxx.h>
35#include <pci.h>
36#include <netdev.h>
37#include <miiphy.h>
38#include <libfdt.h>
39#include <mb862xx.h>
40#include <video_fb.h>
41#include <asm/processor.h>
42#include <asm/io.h>
43
44#ifdef CONFIG_OF_LIBFDT
45#include <fdt_support.h>
46#endif /* CONFIG_OF_LIBFDT */
47
48/* mt46v16m16-75 */
49#ifdef CONFIG_MPC5200_DDR
50/* Settings for XLB = 132 MHz */
51#define SDRAM_MODE 0x018D0000
52#define SDRAM_EMODE 0x40090000
53#define SDRAM_CONTROL 0x714f0f00
54#define SDRAM_CONFIG1 0x73722930
55#define SDRAM_CONFIG2 0x47770000
56#define SDRAM_TAPDELAY 0x10000000
57#else
58#error SDRAM is not supported on this board
59#endif
60
61DECLARE_GLOBAL_DATA_PTR;
62
63static void sdram_start (int hi_addr)
64{
65 struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
66 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
67
68 /* unlock mode register */
69 out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
70
71 /* precharge all banks */
72 out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
73
74 /* set mode register: extended mode */
75 out_be32 (&sdram->mode, SDRAM_EMODE);
76
77 /* set mode register: reset DLL */
78 out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
79
80 /* precharge all banks */
81 out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
82
83 /* auto refresh */
84 out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
85
86 /* set mode register */
87 out_be32 (&sdram->mode, SDRAM_MODE);
88
89 /* normal operation */
90 out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
91}
92
93/*
94 * ATTENTION: Although partially referenced initdram does NOT make real
95 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
96 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
97 */
98
99phys_size_t initdram (int board_type)
100{
101 struct mpc5xxx_mmap_ctl *mmap_ctl =
102 (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
103 struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
104 struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
105 ulong dramsize = 0;
106 ulong dramsize2 = 0;
107 ulong test1, test2;
108
109 /* setup SDRAM chip selects */
110 out_be32 (&mmap_ctl->sdram0, 0x0000001e); /* 2G at 0x0 */
111 out_be32 (&mmap_ctl->sdram1, 0x00000000); /* disabled */
112
113 /* setup config registers */
114 out_be32 (&sdram->config1, SDRAM_CONFIG1);
115 out_be32 (&sdram->config2, SDRAM_CONFIG2);
116
117 /* set tap delay */
118 out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
119
120 /* find RAM size using SDRAM CS0 only */
121 sdram_start (0);
122 test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
123 sdram_start (1);
124 test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
125 if (test1 > test2) {
126 sdram_start (0);
127 dramsize = test1;
128 } else {
129 dramsize = test2;
130 }
131
132 /* memory smaller than 1MB is impossible */
133 if (dramsize < (1 << 20))
134 dramsize = 0;
135
136 /* set SDRAM CS0 size according to the amount of RAM found */
137 if (dramsize > 0)
138 out_be32 (&mmap_ctl->sdram0,
139 0x13 + __builtin_ffs (dramsize >> 20) - 1);
140 else
141 out_be32 (&mmap_ctl->sdram1, 0); /* disabled */
142
143 /*
144 * On MPC5200B we need to set the special configuration delay in the
145 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
146 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
147 *
148 * "The SDelay should be written to a value of 0x00000004. It is
149 * required to account for changes caused by normal wafer processing
150 * parameters."
151 */
152 out_be32 (&sdram->sdelay, 0x04);
153
154 return dramsize + dramsize2;
155}
156
157int checkboard (void)
158{
159 puts ("Board: IPEK01 \n");
160 return 0;
161}
162
163void flash_preinit (void)
164{
165 struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
166
167 /*
168 * Now, when we are in RAM, enable flash write
169 * access for detection process.
170 * Note that CS_BOOT cannot be cleared when
171 * executing in flash.
172 */
173 clrbits_be32 (&lpb->cs0_cfg, 0x1); /* clear RO */
174}
175
176void flash_afterinit (ulong start, ulong size)
177{
178 struct mpc5xxx_mmap_ctl *mmap_ctl =
179 (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
180
181#if defined(CONFIG_BOOT_ROM)
182 /* adjust mapping */
183 out_be32 (&mmap_ctl->cs1_start, START_REG (start));
184 out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
185#else
186 /* adjust mapping */
187 out_be32 (&mmap_ctl->boot_start, START_REG (start));
188 out_be32 (&mmap_ctl->cs0_start, START_REG (start));
189 out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
190 out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
191#endif
192}
193
194extern flash_info_t flash_info[]; /* info for FLASH chips */
195
196int misc_init_r (void)
197{
198 /* adjust flash start */
199 gd->bd->bi_flashstart = flash_info[0].start[0];
200 return (0);
201}
202
203#ifdef CONFIG_PCI
204static struct pci_controller hose;
205
206extern void pci_mpc5xxx_init (struct pci_controller *);
207
208void pci_init_board (void)
209{
210 pci_mpc5xxx_init (&hose);
211}
212#endif
213
214#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
215void ft_board_setup (void *blob, bd_t * bd)
216{
217 ft_cpu_setup (blob, bd);
218 fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
219}
220#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
221
222int board_eth_init(bd_t *bis)
223{
224 cpu_eth_init(bis); /* Built in FEC comes first */
225 return pci_eth_init(bis);
226}
227
228#ifdef CONFIG_VIDEO
229extern GraphicDevice mb862xx;
230
231static const gdc_regs init_regs[] = {
232 {0x0100, 0x00000900},
233 {0x0020, 0x80190257},
234 {0x0024, 0x00000000},
235 {0x0028, 0x00000000},
236 {0x002c, 0x00000000},
237 {0x0110, 0x00000000},
238 {0x0114, 0x00000000},
239 {0x0118, 0x02570320},
240 {0x0004, 0x041f0000},
241 {0x0008, 0x031f031f},
242 {0x000c, 0x067f0347},
243 {0x0010, 0x02780000},
244 {0x0014, 0x0257025c},
245 {0x0018, 0x00000000},
246 {0x001c, 0x02570320},
247 {0x0100, 0x80010900},
248 {0x0, 0x0}
249};
250
251const gdc_regs *board_get_regs (void)
252{
253 return init_regs;
254}
255
256/* Returns Lime base address */
257unsigned int board_video_init (void)
258{
259 if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
260 return 0;
261
262 mb862xx.winSizeX = 800;
263 mb862xx.winSizeY = 600;
264 mb862xx.gdfIndex = GDF_15BIT_555RGB;
265 mb862xx.gdfBytesPP = 2;
266
267 return CONFIG_SYS_LIME_BASE;
268}
269
270#if defined(CONFIG_CONSOLE_EXTRA_INFO)
271/*
272 * Return text to be printed besides the logo.
273 */
274void video_get_info_str (int line_number, char *info)
275{
276 if (line_number == 1)
277 strcpy (info, " Board: IPEK01");
278 else
279 info[0] = '\0';
280}
281#endif
282#endif /* CONFIG_VIDEO */