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wdenk7ca202f2004-08-28 22:45:57 +00001/*
Detlev Zundel69235652007-04-20 12:01:47 +02002 * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
wdenk414eec32005-04-02 22:37:54 +00003 * (C) Copyright 2005
wdenk7ca202f2004-08-28 22:45:57 +00004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config.h - configuration options, board specific
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36#define CONFIG_MPC852T 1
37#define CONFIG_NC650 1
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42#define CONFIG_BAUDRATE 115200
43#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
44
45/*
46 * 10 MHz - PLL input clock
47 */
wdenkcce625e2004-09-28 19:00:19 +000048#define CONFIG_8xx_OSCLK 10000000
wdenk7ca202f2004-08-28 22:45:57 +000049
50/*
51 * 50 MHz - default CPU clock
52 */
wdenk66ca92a2004-09-28 17:59:53 +000053#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
wdenk7ca202f2004-08-28 22:45:57 +000054
55/*
56 * 15 MHz - CPU minimum clock
57 */
wdenk66ca92a2004-09-28 17:59:53 +000058#define CFG_8xx_CPUCLK_MIN 15000000
wdenk7ca202f2004-08-28 22:45:57 +000059
60/*
61 * 133 MHz - CPU maximum clock
62 */
wdenk66ca92a2004-09-28 17:59:53 +000063#define CFG_8xx_CPUCLK_MAX 133000000
wdenk7ca202f2004-08-28 22:45:57 +000064
65#define CFG_MEASURE_CPUCLK
wdenkcce625e2004-09-28 19:00:19 +000066#define CFG_8XX_XIN CONFIG_8xx_OSCLK
wdenk7ca202f2004-08-28 22:45:57 +000067
68#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
dzu@denx.dea367d422006-04-19 11:52:46 +020069#define CONFIG_AUTOBOOT_KEYED
70#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d seconds...\n"
71#define CONFIG_AUTOBOOT_DELAY_STR "ids"
72#define CONFIG_BOOT_RETRY_TIME 900
73#define CONFIG_BOOT_RETRY_MIN 30
wdenk7ca202f2004-08-28 22:45:57 +000074
75#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
76
77#undef CONFIG_BOOTARGS
78#define CONFIG_BOOTCOMMAND \
79 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010080 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
81 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk7ca202f2004-08-28 22:45:57 +000082 "bootm"
83
dzu@denx.dea367d422006-04-19 11:52:46 +020084#define CONFIG_WATCHDOG /* watchdog enabled */
wdenk7ca202f2004-08-28 22:45:57 +000085
86#undef CONFIG_STATUS_LED /* Status LED disabled */
87
Jon Loeliger7be044e2007-07-09 21:24:19 -050088/*
89 * BOOTP options
90 */
91#define CONFIG_BOOTP_SUBNETMASK
92#define CONFIG_BOOTP_GATEWAY
93#define CONFIG_BOOTP_HOSTNAME
94#define CONFIG_BOOTP_BOOTPATH
95#define CONFIG_BOOTP_BOOTFILESIZE
96
wdenk7ca202f2004-08-28 22:45:57 +000097
98#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
99#define FEC_ENET
100#define CONFIG_MII
101#define CFG_DISCOVER_PHY 1
102
103
104/* enable I2C and select the hardware/software driver */
105#undef CONFIG_HARD_I2C /* I2C with hardware support */
106#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
107#define CFG_I2C_SPEED 100000 /* 100 kHz */
108#define CFG_I2C_SLAVE 0x7f
109
110/*
111 * Software (bit-bang) I2C driver configuration
112 */
dzu@denx.dea367d422006-04-19 11:52:46 +0200113#if defined(CONFIG_IDS852_REV1)
114
wdenk4cfaf552004-10-11 23:03:10 +0000115#define SCL 0x1000 /* PA 3 */
116#define SDA 0x2000 /* PA 2 */
wdenk7ca202f2004-08-28 22:45:57 +0000117
Wolfgang Denkf57f70a2005-10-13 01:45:54 +0200118#define __I2C_DIR immr->im_ioport.iop_padir
119#define __I2C_DAT immr->im_ioport.iop_padat
120#define __I2C_PAR immr->im_ioport.iop_papar
dzu@denx.dea367d422006-04-19 11:52:46 +0200121
122#elif defined(CONFIG_IDS852_REV2)
123
124#define SCL 0x0002 /* PB 30 */
125#define SDA 0x0001 /* PB 31 */
126
127#define __I2C_PAR immr->im_cpm.cp_pbpar
128#define __I2C_DIR immr->im_cpm.cp_pbdir
129#define __I2C_DAT immr->im_cpm.cp_pbdat
130
131#endif
132
Wolfgang Denkf57f70a2005-10-13 01:45:54 +0200133#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
134 __I2C_DIR |= (SDA|SCL); }
135#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
136#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
137#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
138#define I2C_DELAY { udelay(5); }
139#define I2C_ACTIVE { __I2C_DIR |= SDA; }
140#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
wdenk7ca202f2004-08-28 22:45:57 +0000141
wdenk4cfaf552004-10-11 23:03:10 +0000142#define CONFIG_RTC_PCF8563
143#define CFG_I2C_RTC_ADDR 0x51
wdenk7ca202f2004-08-28 22:45:57 +0000144
wdenk7ca202f2004-08-28 22:45:57 +0000145
Jon Loeligere18a1062007-07-08 14:21:43 -0500146/*
147 * Command line configuration.
148 */
149#include <config_cmd_default.h>
150
151#define CONFIG_CMD_ASKENV
152#define CONFIG_CMD_DATE
153#define CONFIG_CMD_DHCP
154#define CONFIG_CMD_I2C
155#define CONFIG_CMD_NAND
156#define CONFIG_CMD_JFFS2
157#define CONFIG_CMD_NFS
158#define CONFIG_CMD_SNTP
159
wdenk7ca202f2004-08-28 22:45:57 +0000160
161/*
162 * Miscellaneous configurable options
163 */
164#define CFG_LONGHELP /* undef to save memory */
165#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere18a1062007-07-08 14:21:43 -0500166#if defined(CONFIG_CMD_KGDB)
wdenk7ca202f2004-08-28 22:45:57 +0000167#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
168#else
169#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
170#endif
171#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
172#define CFG_MAXARGS 16 /* max number of command args */
173#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
174
175#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
176#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
177
178#define CFG_LOAD_ADDR 0x00100000
179
180#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
181
182#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
183
184/*
185 * Low Level Configuration Settings
186 * (address mappings, register initial values, etc.)
187 * You should know what you are doing if you make changes here.
188 */
189/*-----------------------------------------------------------------------
190 * Internal Memory Mapped Register
191 */
192#define CFG_IMMR 0xF0000000
193#define CFG_IMMR_SIZE ((uint)(64 * 1024))
194
195/*-----------------------------------------------------------------------
196 * Definitions for initial stack pointer and data area (in DPRAM)
197 */
198#define CFG_INIT_RAM_ADDR CFG_IMMR
199#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
200#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
201#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
202#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
203
204/*-----------------------------------------------------------------------
205 * Start addresses for the final memory configuration
206 * (Set up by the startup code)
207 * Please note that CFG_SDRAM_BASE _must_ start at 0
208 */
209#define CFG_SDRAM_BASE 0x00000000
210#define CFG_FLASH_BASE 0x40000000
211
212#define CFG_RESET_ADDRESS 0xFFF00100
213
214#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
215#define CFG_MONITOR_BASE TEXT_BASE
216#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
217
218/*
219 * For booting Linux, the board info and command line data
220 * have to be in the first 8 MB of memory, since this is
221 * the maximum mapped by the Linux kernel during initialization.
222 */
223#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
224/*-----------------------------------------------------------------------
225 * FLASH organization
226 */
227#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
228#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
229
230#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
231#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
232
233
234#define CFG_ENV_IS_IN_FLASH 1
235#define CFG_ENV_OFFSET 0x00740000
236
237#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
238#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
239
240/*-----------------------------------------------------------------------
241 * Cache Configuration
242 */
243#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere18a1062007-07-08 14:21:43 -0500244#if defined(CONFIG_CMD_KGDB)
wdenk7ca202f2004-08-28 22:45:57 +0000245#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
246#endif
247
wdenk4cfaf552004-10-11 23:03:10 +0000248/*
249 * NAND flash support
250 */
251#define CFG_MAX_NAND_DEVICE 1
wdenk4cfaf552004-10-11 23:03:10 +0000252#define NAND_MAX_CHIPS 1
wdenk4cfaf552004-10-11 23:03:10 +0000253
wdenk7ca202f2004-08-28 22:45:57 +0000254/*-----------------------------------------------------------------------
255 * SYPCR - System Protection Control 11-9
256 * SYPCR can only be written once after reset!
257 *-----------------------------------------------------------------------
258 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
259 */
260#if defined(CONFIG_WATCHDOG)
261#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
262 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
263#else
264#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
265#endif
266
267/*-----------------------------------------------------------------------
268 * SIUMCR - SIU Module Configuration 11-6
269 *-----------------------------------------------------------------------
270 */
271#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
272
273/*-----------------------------------------------------------------------
274 * TBSCR - Time Base Status and Control 11-26
275 *-----------------------------------------------------------------------
276 * Clear Reference Interrupt Status, Timebase freezing enabled
277 */
278#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
279
280/*-----------------------------------------------------------------------
281 * PISCR - Periodic Interrupt Status and Control 11-31
282 *-----------------------------------------------------------------------
283 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
284 */
285#define CFG_PISCR (PISCR_PS | PISCR_PITF)
286
287/*-----------------------------------------------------------------------
288 * SCCR - System Clock and reset Control Register 15-27
289 *-----------------------------------------------------------------------
290 * Set clock output, timebase and RTC source and divider,
291 * power management and some other internal clocks
292 */
293#define SCCR_MASK SCCR_EBDF11
294#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \
295 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
296 SCCR_DFLCD000 | SCCR_DFALCD00)
297
298 /*-----------------------------------------------------------------------
299 *
300 *-----------------------------------------------------------------------
301 *
302 */
303#define CFG_DER 0
304
305/*
306 * Init Memory Controller:
307 *
308 * BR0 and OR0 (FLASH)
309 */
310
311#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
312
313#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
314#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
315
316/* FLASH timing: Default value of OR0 after reset */
317#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
318 OR_SCY_15_CLK | OR_TRLX)
319
320#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
321#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
322#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
323
324/*
dzu@denx.dea367d422006-04-19 11:52:46 +0200325 * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
326 * rev2 only uses the chipselect
wdenk4cfaf552004-10-11 23:03:10 +0000327 */
328#define CFG_NAND_BASE 0x50000000
329#define CFG_NAND_SIZE 0x04000000
330
331#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
332 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
333
wdenkc3fafec2005-03-14 23:01:03 +0000334#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V )
wdenk8f0b7cb2005-03-27 23:41:39 +0000335#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )
wdenk4cfaf552004-10-11 23:03:10 +0000336
337/*
wdenk7ca202f2004-08-28 22:45:57 +0000338 * BR3 and OR3 (SDRAM)
339 */
340#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
341#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
342
343 /*
344 * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
345 */
346#define CFG_OR_TIMING_SDRAM 0x00000A00
347
348#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
349#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
350
351/*
dzu@denx.dea367d422006-04-19 11:52:46 +0200352 * BR4 and OR4 (CPLD)
353 */
354#define CFG_CPLD_BASE 0x80000000 /* CPLD */
355#define CFG_CPLD_SIZE 0x10000 /* only 16 used */
356
357#define CFG_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
358 OR_SCY_1_CLK)
359
360#define CFG_BR4_PRELIM ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
361#define CFG_OR4_PRELIM (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD)
362
363/*
wdenkcacfab52004-11-17 20:44:20 +0000364 * BR5 and OR5 (SRAM)
365 */
366#define CFG_SRAM_BASE 0x60000000
367#define CFG_SRAM_SIZE 0x00080000
368
369#define CFG_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
370 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
371
372#define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
373#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
374
dzu@denx.dea367d422006-04-19 11:52:46 +0200375#if defined(CONFIG_CP850)
376/*
377 * BR6 and OR6 (DPRAM) - only on CP850
378 */
379#define CFG_OR6_PRELIM 0xffff8170
380#define CFG_BR6_PRELIM 0xa0000401
381#define DPRAM_BASE_ADDR 0xa0000000
382
383#define CONFIG_MISC_INIT_R 1
384#endif
wdenkcacfab52004-11-17 20:44:20 +0000385
wdenkcacfab52004-11-17 20:44:20 +0000386/*
wdenk7ca202f2004-08-28 22:45:57 +0000387 * 4096 Rows from SDRAM example configuration
388 * 1000 factor s -> ms
389 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
390 * 4 Number of refresh cycles per period
391 * 64 Refresh cycle in ms per number of rows
392 */
wdenk66ca92a2004-09-28 17:59:53 +0000393#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
wdenk7ca202f2004-08-28 22:45:57 +0000394
395/*
396 * Memory Periodic Timer Prescaler
397 */
398
399/* periodic timer for refresh */
400#define CFG_MAMR_PTA 39
401
402/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
403#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
404#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
405
406/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
407#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
408#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
409
410/*
411 * MAMR settings for SDRAM
412 */
413
414#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
415 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
416 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
417#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
418 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
419 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
420
421/*
wdenkc3fafec2005-03-14 23:01:03 +0000422 * MBMR settings for NAND flash
423 */
424
425#define CFG_MBMR_NAND ( MBMR_WLFB_5X )
426
427/*
wdenk7ca202f2004-08-28 22:45:57 +0000428 * Internal Definitions
429 *
430 * Boot Flags
431 */
432#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
433#define BOOTFLAG_WARM 0x02 /* Software reboot */
434
wdenk07cc0992005-05-05 00:04:14 +0000435#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
wdenk07cc0992005-05-05 00:04:14 +0000436#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
wdenk7ca202f2004-08-28 22:45:57 +0000437
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200438/*
439 * JFFS2 partitions
440 */
441
442/* No command line, one static partition */
443#undef CONFIG_JFFS2_CMDLINE
444#define CONFIG_JFFS2_DEV "nand0"
445#define CONFIG_JFFS2_PART_SIZE 0x00400000
446#define CONFIG_JFFS2_PART_OFFSET 0x00000000
447
448/* mtdparts command line support */
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200449#define CONFIG_JFFS2_CMDLINE
450#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand"
451
452#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
dzu@denx.dea367d422006-04-19 11:52:46 +0200453 "4m(cramfs1),1m(cramfs2)," \
454 "256k(u-boot),128k(env);" \
455 "nc650-nand:4m(jffs1),28m(jffs2)"
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200456
wdenk7ca202f2004-08-28 22:45:57 +0000457#endif /* __CONFIG_H */