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wdenk6310eb92005-01-09 21:28:15 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuration settings for the PLEB 2 board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenk6310eb92005-01-09 21:28:15 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
38#define CONFIG_PLEB2 1 /* on an PLEB2 Board */
39#undef CONFIG_LCD
40#undef CONFIG_MMC
41#define BOARD_LATE_INIT 1
42
43#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44
45/*
46 * Size of malloc() pool
47 */
48#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
49#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
50
51/*
52 * Hardware drivers
53 */
54
55/* None - PLEB 2 doesn't have any of this.
56 #define CONFIG_DRIVER_LAN91C96
57 #define CONFIG_LAN91C96_BASE 0x0C000000 */
58
59/*
60 * select serial console configuration
61 */
62#define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */
63
64/* allow to overwrite serial and ethaddr */
65#define CONFIG_ENV_OVERWRITE
66
67#define CONFIG_BAUDRATE 115200
68
wdenk6310eb92005-01-09 21:28:15 +000069
Jon Loeliger26a34562007-07-04 22:33:17 -050070/*
Jon Loeliger079a1362007-07-10 10:12:10 -050071 * BOOTP options
72 */
73#define CONFIG_BOOTP_BOOTFILESIZE
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77
78
79/*
Jon Loeliger26a34562007-07-04 22:33:17 -050080 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
84#undef CONFIG_CMD_NET
85
wdenk6310eb92005-01-09 21:28:15 +000086
87#define CONFIG_BOOTDELAY 3
88#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
89#define CONFIG_NETMASK 255.255.0.0
90#define CONFIG_IPADDR 192.168.0.21
91#define CONFIG_SERVERIP 192.168.0.250
92#define CONFIG_BOOTCOMMAND "bootm 40000"
93#define CONFIG_BOOTARGS "root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200"
94
95#define CONFIG_CMDLINE_TAG
96#define CONFIG_INITRD_TAG
97#define CONFIG_SETUP_MEMORY_TAGS
98
Jon Loeliger26a34562007-07-04 22:33:17 -050099#if defined(CONFIG_CMD_KGDB)
wdenk6310eb92005-01-09 21:28:15 +0000100#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
101#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
102#endif
103
104/*
105 * Miscellaneous configurable options
106 */
107#define CFG_HUSH_PARSER 1
108#define CFG_PROMPT_HUSH_PS2 "> "
109
110#define CFG_LONGHELP /* undef to save memory */
111#ifdef CFG_HUSH_PARSER
112#define CFG_PROMPT "$ " /* Monitor Command Prompt */
113#else
114#define CFG_PROMPT "=> " /* Monitor Command Prompt */
115#endif
116#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
117#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
118#define CFG_MAXARGS 16 /* max number of command args */
119#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
120#define CFG_DEVICE_NULLDEV 1
121
122#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
123#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
124
125#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
126
127#define CFG_LOAD_ADDR 0xa2000000 /* default load address */
128
129#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
130#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
131
132 /* valid baudrates */
133#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
134
135/*
136 * Stack sizes
137 *
138 * The stack sizes are set up in start.S using the settings below
139 */
140#define CONFIG_STACKSIZE (128*1024) /* regular stack */
141#ifdef CONFIG_USE_IRQ
142#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
143#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
144#endif
145
146/*
147 * Physical Memory Map
148 */
149#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
150#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
151#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
152#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
153#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
154#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
155#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
156#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
157#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
158
159#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
160#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
161#define PHYS_FLASH_SIZE 0x00800000 /* 4 MB */
162
163/* Not entirely sure about this - DS/CHC */
164#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
165#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
166
167#define CFG_DRAM_BASE PHYS_SDRAM_1
168#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
169
170#define CFG_FLASH_BASE PHYS_FLASH_1
171#define CFG_MONITOR_BASE CFG_FLASH_BASE
172
173/*
174 * GPIO settings
175 */
176#define CFG_GPSR0_VAL 0x00000000 /* Don't set anything */
177#define CFG_GPSR1_VAL 0x00000080
178#define CFG_GPSR2_VAL 0x00000000
179
180#define CFG_GPCR0_VAL 0x00000000 /* Don't clear anything */
181#define CFG_GPCR1_VAL 0x00000000
182#define CFG_GPCR2_VAL 0x00000000
183
184#define CFG_GPDR0_VAL 0x00000000
185#define CFG_GPDR1_VAL 0x000007C3
186#define CFG_GPDR2_VAL 0x00000000
187
188/* Edge detect registers (these are set by the kernel) */
189#define CFG_GRER0_VAL 0x00000000
190#define CFG_GRER1_VAL 0x00000000
191#define CFG_GRER2_VAL 0x00000000
192#define CFG_GFER0_VAL 0x00000000
193#define CFG_GFER1_VAL 0x00000000
194#define CFG_GFER2_VAL 0x00000000
195
196#define CFG_GAFR0_L_VAL 0x00000000
197#define CFG_GAFR0_U_VAL 0x00000000
198#define CFG_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */
199#define CFG_GAFR1_U_VAL 0x00000000
200#define CFG_GAFR2_L_VAL 0x00000000
201#define CFG_GAFR2_U_VAL 0x00000000
202
203#define CFG_PSSR_VAL 0x20
204#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
205#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
206#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
207
208/*
209 * Memory settings
210 */
211#define CFG_MSC0_VAL 0x00007FF0 /* Not properly calculated - FIXME (DS) */
212#define CFG_MSC1_VAL 0x00000000
213#define CFG_MSC2_VAL 0x00000000
214
215#define CFG_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM.
216 tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */
217
wdenk400558b2005-04-02 23:52:25 +0000218#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual */
219 /* bits set in lowlevel_init.S */
wdenk6310eb92005-01-09 21:28:15 +0000220#define CFG_MDMRS_VAL 0x00000000
221
222/*
223 * PCMCIA and CF Interfaces
224 */
225#define CFG_MECR_VAL 0x00000000 /* Hangover from Lubbock.
226 Needs calculating. (DS/CHC) */
227#define CFG_MCMEM0_VAL 0x00010504
228#define CFG_MCMEM1_VAL 0x00010504
229#define CFG_MCATT0_VAL 0x00010504
230#define CFG_MCATT1_VAL 0x00010504
231#define CFG_MCIO0_VAL 0x00004715
232#define CFG_MCIO1_VAL 0x00004715
233
234/*
235 * FLASH and environment organization
236 */
237#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
238#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
239
240/* timeout values are in ticks */
241/* FIXME */
242#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
243#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
244
245/* Flash protection */
246#define CFG_FLASH_PROTECTION 1
247
248/* FIXME */
249#define CFG_ENV_IS_IN_FLASH 1
250#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */
251#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
252#define CFG_ENV_SECT_SIZE 0x20000
253
254/* Option added to get around byte ordering issues in the flash driver */
255#define CFG_LITTLE_ENDIAN 1
256
257#endif /* __CONFIG_H */