blob: 4328feb4e36b55ccc67e84489077df46fd438a52 [file] [log] [blame]
wdenk074cff02004-02-24 00:16:43 +00001/*
2 * (C) Copyright 2004
3 * DAVE Srl
4 * http://www.dave-tech.it
5 * http://www.wawnet.biz
6 * mailto:info@wawnet.biz
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/hardware.h>
29
30#include <asm/proc-armv/ptrace.h>
31
32extern void reset_cpu(ulong addr);
33
34/* we always count down the max. */
35#define TIMER_LOAD_VAL 0xffff
36
37/* macro to read the 16 bit timer */
38#define READ_TIMER (TCNTO1 & 0xffff)
39
40#ifdef CONFIG_USE_IRQ
41#error CONFIG_USE_IRQ NOT supported
42#else
43void enable_interrupts (void)
44{
45 return;
46}
47int disable_interrupts (void)
48{
49 return 0;
50}
51#endif
52
53
54void bad_mode (void)
55{
56 panic ("Resetting CPU ...\n");
57 reset_cpu (0);
58}
59
60void show_regs (struct pt_regs *regs)
61{
62 unsigned long flags;
63 const char *processor_modes[] =
64 { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
65 "UK6_26", "UK7_26",
66 "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
67 "UK14_26", "UK15_26",
68 "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
69 "UK6_32", "ABT_32",
70 "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
71 "UK14_32", "SYS_32"
72 };
73
74 flags = condition_codes (regs);
75
76 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
77 "sp : %08lx ip : %08lx fp : %08lx\n",
78 instruction_pointer (regs),
79 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
80 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
81 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
82 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
83 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
84 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
85 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
86 printf ("Flags: %c%c%c%c",
87 flags & CC_N_BIT ? 'N' : 'n',
88 flags & CC_Z_BIT ? 'Z' : 'z',
89 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
90 printf (" IRQs %s FIQs %s Mode %s%s\n",
91 interrupts_enabled (regs) ? "on" : "off",
92 fast_interrupts_enabled (regs) ? "on" : "off",
93 processor_modes[processor_mode (regs)],
94 thumb_mode (regs) ? " (T)" : "");
95}
96
97void do_undefined_instruction (struct pt_regs *pt_regs)
98{
99 printf ("undefined instruction\n");
100 show_regs (pt_regs);
101 bad_mode ();
102}
103
104void do_software_interrupt (struct pt_regs *pt_regs)
105{
106 printf ("software interrupt\n");
107 show_regs (pt_regs);
108 bad_mode ();
109}
110
111void do_prefetch_abort (struct pt_regs *pt_regs)
112{
113 printf ("prefetch abort\n");
114 show_regs (pt_regs);
115 bad_mode ();
116}
117
118void do_data_abort (struct pt_regs *pt_regs)
119{
120 printf ("data abort\n");
121 show_regs (pt_regs);
122 bad_mode ();
123}
124
125void do_not_used (struct pt_regs *pt_regs)
126{
127 printf ("not used\n");
128 show_regs (pt_regs);
129 bad_mode ();
130}
131
132void do_fiq (struct pt_regs *pt_regs)
133{
134 printf ("fast interrupt request\n");
135 show_regs (pt_regs);
136 bad_mode ();
137}
138
139void do_irq (struct pt_regs *pt_regs)
140{
141 printf ("interrupt request\n");
142 show_regs (pt_regs);
143 bad_mode ();
144}
145
146static ulong timestamp;
147static ulong lastdec;
148
149int interrupt_init (void)
150{
151 TCFG0 = 0x000000E9;
152 TCFG1 = 0x00000004;
153 TCON = 0x00000900;
154 TCNTB1 = TIMER_LOAD_VAL;
155 TCMPB1 = 0;
156 TCON = 0x00000B00;
157 TCON = 0x00000900;
158
159
160 lastdec = TCNTB1 = TIMER_LOAD_VAL;
161 timestamp = 0;
162 return 0;
163}
164
165/*
166 * timer without interrupts
167 */
168
169void reset_timer (void)
170{
171 reset_timer_masked ();
172}
173
174ulong get_timer (ulong base)
175{
176 return get_timer_masked () - base;
177}
178
179void set_timer (ulong t)
180{
181 timestamp = t;
182}
183
184void udelay (unsigned long usec)
185{
186 ulong tmo;
187
188 tmo = usec / 1000;
189 tmo *= CFG_HZ;
190 tmo /= 8;
191
192 tmo += get_timer (0);
193
194 while (get_timer_masked () < tmo)
195 /*NOP*/;
196}
197
198void reset_timer_masked (void)
199{
200 /* reset time */
201 lastdec = READ_TIMER;
202 timestamp = 0;
203}
204
205ulong get_timer_masked (void)
206{
207 ulong now = READ_TIMER;
208
209 if (lastdec >= now) {
210 /* normal mode */
211 timestamp += lastdec - now;
212 } else {
213 /* we have an overflow ... */
214 timestamp += lastdec + TIMER_LOAD_VAL - now;
215 }
216 lastdec = now;
217
218 return timestamp;
219}
220
221void udelay_masked (unsigned long usec)
222{
223 ulong tmo;
224
225 tmo = usec / 1000;
226 tmo *= CFG_HZ;
227 tmo /= 8;
228
229 tmo += get_timer (0);
230
231 reset_timer_masked ();
232
233 while (get_timer_masked () < tmo)
234 /*NOP*/;
235}