blob: 192be7dfa1d1e81c939db1499178fa5777a12357 [file] [log] [blame]
Chin Liang See3eb3e722014-09-12 00:42:17 -05001/*
2 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
4 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <malloc.h>
11#include <nand.h>
12#include <asm/errno.h>
13#include <asm/io.h>
14
15#include "denali.h"
16
17#define NAND_DEFAULT_TIMINGS -1
18
19static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
20
Scott Woodd3963722015-06-26 19:03:26 -050021/*
22 * We define a macro here that combines all interrupts this driver uses into
23 * a single constant value, for convenience.
24 */
Chin Liang See3eb3e722014-09-12 00:42:17 -050025#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
26 INTR_STATUS__ECC_TRANSACTION_DONE | \
27 INTR_STATUS__ECC_ERR | \
28 INTR_STATUS__PROGRAM_FAIL | \
29 INTR_STATUS__LOAD_COMP | \
30 INTR_STATUS__PROGRAM_COMP | \
31 INTR_STATUS__TIME_OUT | \
32 INTR_STATUS__ERASE_FAIL | \
33 INTR_STATUS__RST_COMP | \
34 INTR_STATUS__ERASE_COMP | \
35 INTR_STATUS__ECC_UNCOR_ERR | \
36 INTR_STATUS__INT_ACT | \
37 INTR_STATUS__LOCKED_BLK)
38
Scott Woodd3963722015-06-26 19:03:26 -050039/*
40 * indicates whether or not the internal value for the flash bank is
41 * valid or not
42 */
Chin Liang See3eb3e722014-09-12 00:42:17 -050043#define CHIP_SELECT_INVALID -1
44
45#define SUPPORT_8BITECC 1
46
47/*
48 * this macro allows us to convert from an MTD structure to our own
49 * device context (denali) structure.
50 */
Masahiro Yamada65e41452014-11-13 20:31:50 +090051#define mtd_to_denali(m) container_of(m->priv, struct denali_nand_info, nand)
Chin Liang See3eb3e722014-09-12 00:42:17 -050052
Scott Woodd3963722015-06-26 19:03:26 -050053/*
54 * These constants are defined by the driver to enable common driver
55 * configuration options.
56 */
Chin Liang See3eb3e722014-09-12 00:42:17 -050057#define SPARE_ACCESS 0x41
58#define MAIN_ACCESS 0x42
59#define MAIN_SPARE_ACCESS 0x43
Scott Woodd3963722015-06-26 19:03:26 -050060#define PIPELINE_ACCESS 0x2000
Chin Liang See3eb3e722014-09-12 00:42:17 -050061
62#define DENALI_UNLOCK_START 0x10
63#define DENALI_UNLOCK_END 0x11
64#define DENALI_LOCK 0x21
65#define DENALI_LOCK_TIGHT 0x31
66#define DENALI_BUFFER_LOAD 0x60
67#define DENALI_BUFFER_WRITE 0x62
68
69#define DENALI_READ 0
70#define DENALI_WRITE 0x100
71
72/* types of device accesses. We can issue commands and get status */
73#define COMMAND_CYCLE 0
74#define ADDR_CYCLE 1
75#define STATUS_CYCLE 2
76
Scott Woodd3963722015-06-26 19:03:26 -050077/*
78 * this is a helper macro that allows us to
79 * format the bank into the proper bits for the controller
80 */
Chin Liang See3eb3e722014-09-12 00:42:17 -050081#define BANK(x) ((x) << 24)
82
83/* Interrupts are cleared by writing a 1 to the appropriate status bit */
84static inline void clear_interrupt(struct denali_nand_info *denali,
85 uint32_t irq_mask)
86{
87 uint32_t intr_status_reg;
88
89 intr_status_reg = INTR_STATUS(denali->flash_bank);
90
91 writel(irq_mask, denali->flash_reg + intr_status_reg);
92}
93
94static uint32_t read_interrupt_status(struct denali_nand_info *denali)
95{
96 uint32_t intr_status_reg;
97
98 intr_status_reg = INTR_STATUS(denali->flash_bank);
99
100 return readl(denali->flash_reg + intr_status_reg);
101}
102
103static void clear_interrupts(struct denali_nand_info *denali)
104{
105 uint32_t status;
106
107 status = read_interrupt_status(denali);
108 clear_interrupt(denali, status);
109
110 denali->irq_status = 0;
111}
112
113static void denali_irq_enable(struct denali_nand_info *denali,
114 uint32_t int_mask)
115{
116 int i;
117
118 for (i = 0; i < denali->max_banks; ++i)
119 writel(int_mask, denali->flash_reg + INTR_EN(i));
120}
121
122static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
123{
124 unsigned long timeout = 1000000;
125 uint32_t intr_status;
126
127 do {
128 intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL;
129 if (intr_status & irq_mask) {
130 denali->irq_status &= ~irq_mask;
131 /* our interrupt was detected */
132 break;
133 }
134 udelay(1);
135 timeout--;
136 } while (timeout != 0);
137
138 if (timeout == 0) {
139 /* timeout */
140 printf("Denali timeout with interrupt status %08x\n",
141 read_interrupt_status(denali));
142 intr_status = 0;
143 }
144 return intr_status;
145}
146
147/*
148 * Certain operations for the denali NAND controller use an indexed mode to
149 * read/write data. The operation is performed by writing the address value
150 * of the command to the device memory followed by the data. This function
151 * abstracts this common operation.
Scott Woodd3963722015-06-26 19:03:26 -0500152 */
Chin Liang See3eb3e722014-09-12 00:42:17 -0500153static void index_addr(struct denali_nand_info *denali,
154 uint32_t address, uint32_t data)
155{
156 writel(address, denali->flash_mem + INDEX_CTRL_REG);
157 writel(data, denali->flash_mem + INDEX_DATA_REG);
158}
159
160/* Perform an indexed read of the device */
161static void index_addr_read_data(struct denali_nand_info *denali,
162 uint32_t address, uint32_t *pdata)
163{
164 writel(address, denali->flash_mem + INDEX_CTRL_REG);
165 *pdata = readl(denali->flash_mem + INDEX_DATA_REG);
166}
167
Scott Woodd3963722015-06-26 19:03:26 -0500168/*
169 * We need to buffer some data for some of the NAND core routines.
170 * The operations manage buffering that data.
171 */
Chin Liang See3eb3e722014-09-12 00:42:17 -0500172static void reset_buf(struct denali_nand_info *denali)
173{
174 denali->buf.head = 0;
175 denali->buf.tail = 0;
176}
177
178static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
179{
180 denali->buf.buf[denali->buf.tail++] = byte;
181}
182
183/* resets a specific device connected to the core */
184static void reset_bank(struct denali_nand_info *denali)
185{
186 uint32_t irq_status;
Scott Woodd3963722015-06-26 19:03:26 -0500187 uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
Chin Liang See3eb3e722014-09-12 00:42:17 -0500188
189 clear_interrupts(denali);
190
191 writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
192
193 irq_status = wait_for_irq(denali, irq_mask);
194 if (irq_status & INTR_STATUS__TIME_OUT)
195 debug("reset bank failed.\n");
196}
197
198/* Reset the flash controller */
199static uint32_t denali_nand_reset(struct denali_nand_info *denali)
200{
Scott Woodd3963722015-06-26 19:03:26 -0500201 int i;
Chin Liang See3eb3e722014-09-12 00:42:17 -0500202
203 for (i = 0; i < denali->max_banks; i++)
204 writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
205 denali->flash_reg + INTR_STATUS(i));
206
207 for (i = 0; i < denali->max_banks; i++) {
208 writel(1 << i, denali->flash_reg + DEVICE_RESET);
209 while (!(readl(denali->flash_reg + INTR_STATUS(i)) &
210 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
211 if (readl(denali->flash_reg + INTR_STATUS(i)) &
212 INTR_STATUS__TIME_OUT)
213 debug("NAND Reset operation timed out on bank"
214 " %d\n", i);
215 }
216
217 for (i = 0; i < denali->max_banks; i++)
218 writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
219 denali->flash_reg + INTR_STATUS(i));
220
221 return 0;
222}
223
224/*
225 * this routine calculates the ONFI timing values for a given mode and
226 * programs the clocking register accordingly. The mode is determined by
227 * the get_onfi_nand_para routine.
228 */
229static void nand_onfi_timing_set(struct denali_nand_info *denali,
230 uint16_t mode)
231{
232 uint32_t trea[6] = {40, 30, 25, 20, 20, 16};
233 uint32_t trp[6] = {50, 25, 17, 15, 12, 10};
234 uint32_t treh[6] = {30, 15, 15, 10, 10, 7};
235 uint32_t trc[6] = {100, 50, 35, 30, 25, 20};
236 uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15};
237 uint32_t trloh[6] = {0, 0, 0, 0, 5, 5};
238 uint32_t tcea[6] = {100, 45, 30, 25, 25, 25};
239 uint32_t tadl[6] = {200, 100, 100, 100, 70, 70};
240 uint32_t trhw[6] = {200, 100, 100, 100, 100, 100};
241 uint32_t trhz[6] = {200, 100, 100, 100, 100, 100};
242 uint32_t twhr[6] = {120, 80, 80, 60, 60, 60};
243 uint32_t tcs[6] = {70, 35, 25, 25, 20, 15};
244
Chin Liang See3eb3e722014-09-12 00:42:17 -0500245 uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
246 uint32_t dv_window = 0;
247 uint32_t en_lo, en_hi;
248 uint32_t acc_clks;
249 uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
250
251 en_lo = DIV_ROUND_UP(trp[mode], CLK_X);
252 en_hi = DIV_ROUND_UP(treh[mode], CLK_X);
253 if ((en_hi * CLK_X) < (treh[mode] + 2))
254 en_hi++;
255
256 if ((en_lo + en_hi) * CLK_X < trc[mode])
257 en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X),
258 CLK_X);
259
260 if ((en_lo + en_hi) < CLK_MULTI)
261 en_lo += CLK_MULTI - en_lo - en_hi;
262
263 while (dv_window < 8) {
264 data_invalid_rhoh = en_lo * CLK_X + trhoh[mode];
265
266 data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode];
267
Scott Woodd3963722015-06-26 19:03:26 -0500268 data_invalid = data_invalid_rhoh < data_invalid_rloh ?
269 data_invalid_rhoh : data_invalid_rloh;
Chin Liang See3eb3e722014-09-12 00:42:17 -0500270
271 dv_window = data_invalid - trea[mode];
272
273 if (dv_window < 8)
274 en_lo++;
275 }
276
277 acc_clks = DIV_ROUND_UP(trea[mode], CLK_X);
278
Scott Woodd3963722015-06-26 19:03:26 -0500279 while (acc_clks * CLK_X - trea[mode] < 3)
Chin Liang See3eb3e722014-09-12 00:42:17 -0500280 acc_clks++;
281
Scott Woodd3963722015-06-26 19:03:26 -0500282 if (data_invalid - acc_clks * CLK_X < 2)
Chin Liang See3eb3e722014-09-12 00:42:17 -0500283 debug("%s, Line %d: Warning!\n", __FILE__, __LINE__);
284
285 addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X);
286 re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X);
287 re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X);
288 we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X);
289 cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X);
Chin Liang See3eb3e722014-09-12 00:42:17 -0500290 if (cs_cnt == 0)
291 cs_cnt = 1;
292
293 if (tcea[mode]) {
Scott Woodd3963722015-06-26 19:03:26 -0500294 while (cs_cnt * CLK_X + trea[mode] < tcea[mode])
Chin Liang See3eb3e722014-09-12 00:42:17 -0500295 cs_cnt++;
296 }
297
298 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
Scott Woodd3963722015-06-26 19:03:26 -0500299 if (readl(denali->flash_reg + MANUFACTURER_ID) == 0 &&
300 readl(denali->flash_reg + DEVICE_ID) == 0x88)
Chin Liang See3eb3e722014-09-12 00:42:17 -0500301 acc_clks = 6;
302
303 writel(acc_clks, denali->flash_reg + ACC_CLKS);
304 writel(re_2_we, denali->flash_reg + RE_2_WE);
305 writel(re_2_re, denali->flash_reg + RE_2_RE);
306 writel(we_2_re, denali->flash_reg + WE_2_RE);
307 writel(addr_2_data, denali->flash_reg + ADDR_2_DATA);
308 writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
309 writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
310 writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
311}
312
313/* queries the NAND device to see what ONFI modes it supports. */
314static uint32_t get_onfi_nand_para(struct denali_nand_info *denali)
315{
316 int i;
Scott Woodd3963722015-06-26 19:03:26 -0500317
Chin Liang See3eb3e722014-09-12 00:42:17 -0500318 /*
319 * we needn't to do a reset here because driver has already
320 * reset all the banks before
321 */
322 if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) &
323 ONFI_TIMING_MODE__VALUE))
324 return -EIO;
325
326 for (i = 5; i > 0; i--) {
327 if (readl(denali->flash_reg + ONFI_TIMING_MODE) &
328 (0x01 << i))
329 break;
330 }
331
332 nand_onfi_timing_set(denali, i);
333
Scott Woodd3963722015-06-26 19:03:26 -0500334 /*
335 * By now, all the ONFI devices we know support the page cache
336 * rw feature. So here we enable the pipeline_rw_ahead feature
337 */
338
Chin Liang See3eb3e722014-09-12 00:42:17 -0500339 return 0;
340}
341
342static void get_samsung_nand_para(struct denali_nand_info *denali,
343 uint8_t device_id)
344{
345 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
346 /* Set timing register values according to datasheet */
347 writel(5, denali->flash_reg + ACC_CLKS);
348 writel(20, denali->flash_reg + RE_2_WE);
349 writel(12, denali->flash_reg + WE_2_RE);
350 writel(14, denali->flash_reg + ADDR_2_DATA);
351 writel(3, denali->flash_reg + RDWR_EN_LO_CNT);
352 writel(2, denali->flash_reg + RDWR_EN_HI_CNT);
353 writel(2, denali->flash_reg + CS_SETUP_CNT);
354 }
355}
356
357static void get_toshiba_nand_para(struct denali_nand_info *denali)
358{
359 uint32_t tmp;
360
Scott Woodd3963722015-06-26 19:03:26 -0500361 /*
362 * Workaround to fix a controller bug which reports a wrong
363 * spare area size for some kind of Toshiba NAND device
364 */
Chin Liang See3eb3e722014-09-12 00:42:17 -0500365 if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
366 (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
367 writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
368 tmp = readl(denali->flash_reg + DEVICES_CONNECTED) *
369 readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
370 writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
371 }
372}
373
374static void get_hynix_nand_para(struct denali_nand_info *denali,
375 uint8_t device_id)
376{
377 uint32_t main_size, spare_size;
378
379 switch (device_id) {
380 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
381 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
382 writel(128, denali->flash_reg + PAGES_PER_BLOCK);
383 writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
384 writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
385 main_size = 4096 *
386 readl(denali->flash_reg + DEVICES_CONNECTED);
387 spare_size = 224 *
388 readl(denali->flash_reg + DEVICES_CONNECTED);
389 writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
390 writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
391 writel(0, denali->flash_reg + DEVICE_WIDTH);
392 break;
393 default:
Scott Woodd3963722015-06-26 19:03:26 -0500394 debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
Chin Liang See3eb3e722014-09-12 00:42:17 -0500395 "Will use default parameter values instead.\n",
396 device_id);
397 }
398}
399
400/*
401 * determines how many NAND chips are connected to the controller. Note for
402 * Intel CE4100 devices we don't support more than one device.
403 */
404static void find_valid_banks(struct denali_nand_info *denali)
405{
406 uint32_t id[denali->max_banks];
407 int i;
408
409 denali->total_used_banks = 1;
410 for (i = 0; i < denali->max_banks; i++) {
Scott Woodd3963722015-06-26 19:03:26 -0500411 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
412 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
413 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
Chin Liang See3eb3e722014-09-12 00:42:17 -0500414
415 if (i == 0) {
416 if (!(id[i] & 0x0ff))
417 break;
418 } else {
419 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
420 denali->total_used_banks++;
421 else
422 break;
423 }
424 }
425}
426
427/*
428 * Use the configuration feature register to determine the maximum number of
429 * banks that the hardware supports.
430 */
431static void detect_max_banks(struct denali_nand_info *denali)
432{
433 uint32_t features = readl(denali->flash_reg + FEATURES);
434 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
435}
436
437static void detect_partition_feature(struct denali_nand_info *denali)
438{
439 /*
440 * For MRST platform, denali->fwblks represent the
441 * number of blocks firmware is taken,
442 * FW is in protect partition and MTD driver has no
443 * permission to access it. So let driver know how many
444 * blocks it can't touch.
445 */
446 if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
447 if ((readl(denali->flash_reg + PERM_SRC_ID(1)) &
448 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
449 denali->fwblks =
450 ((readl(denali->flash_reg + MIN_MAX_BANK(1)) &
451 MIN_MAX_BANK__MIN_VALUE) *
452 denali->blksperchip)
453 +
454 (readl(denali->flash_reg + MIN_BLK_ADDR(1)) &
455 MIN_BLK_ADDR__VALUE);
456 } else {
457 denali->fwblks = SPECTRA_START_BLOCK;
458 }
459 } else {
460 denali->fwblks = SPECTRA_START_BLOCK;
461 }
462}
463
464static uint32_t denali_nand_timing_set(struct denali_nand_info *denali)
465{
Scott Woodd3963722015-06-26 19:03:26 -0500466 uint32_t id_bytes[8], addr;
467 uint8_t maf_id, device_id;
468 int i;
Chin Liang See3eb3e722014-09-12 00:42:17 -0500469
Scott Woodd3963722015-06-26 19:03:26 -0500470 /*
471 * Use read id method to get device ID and other params.
472 * For some NAND chips, controller can't report the correct
473 * device ID by reading from DEVICE_ID register
474 */
475 addr = MODE_11 | BANK(denali->flash_bank);
476 index_addr(denali, addr | 0, 0x90);
477 index_addr(denali, addr | 1, 0);
478 for (i = 0; i < 8; i++)
Chin Liang See3eb3e722014-09-12 00:42:17 -0500479 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
480 maf_id = id_bytes[0];
481 device_id = id_bytes[1];
482
483 if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
484 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
485 if (get_onfi_nand_para(denali))
486 return -EIO;
487 } else if (maf_id == 0xEC) { /* Samsung NAND */
488 get_samsung_nand_para(denali, device_id);
489 } else if (maf_id == 0x98) { /* Toshiba NAND */
490 get_toshiba_nand_para(denali);
491 } else if (maf_id == 0xAD) { /* Hynix NAND */
492 get_hynix_nand_para(denali, device_id);
493 }
494
495 find_valid_banks(denali);
496
497 detect_partition_feature(denali);
498
Scott Woodd3963722015-06-26 19:03:26 -0500499 /*
500 * If the user specified to override the default timings
Chin Liang See3eb3e722014-09-12 00:42:17 -0500501 * with a specific ONFI mode, we apply those changes here.
502 */
503 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
504 nand_onfi_timing_set(denali, onfi_timing_mode);
505
506 return 0;
507}
508
Scott Woodd3963722015-06-26 19:03:26 -0500509/*
510 * validation function to verify that the controlling software is making
Chin Liang See3eb3e722014-09-12 00:42:17 -0500511 * a valid request
512 */
513static inline bool is_flash_bank_valid(int flash_bank)
514{
515 return flash_bank >= 0 && flash_bank < 4;
516}
517
518static void denali_irq_init(struct denali_nand_info *denali)
519{
Scott Woodd3963722015-06-26 19:03:26 -0500520 uint32_t int_mask;
Chin Liang See3eb3e722014-09-12 00:42:17 -0500521 int i;
522
523 /* Disable global interrupts */
524 writel(0, denali->flash_reg + GLOBAL_INT_ENABLE);
525
526 int_mask = DENALI_IRQ_ALL;
527
528 /* Clear all status bits */
529 for (i = 0; i < denali->max_banks; ++i)
530 writel(0xFFFF, denali->flash_reg + INTR_STATUS(i));
531
532 denali_irq_enable(denali, int_mask);
533}
534
Scott Woodd3963722015-06-26 19:03:26 -0500535/*
536 * This helper function setups the registers for ECC and whether or not
537 * the spare area will be transferred.
538 */
Chin Liang See3eb3e722014-09-12 00:42:17 -0500539static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
540 bool transfer_spare)
541{
Scott Woodd3963722015-06-26 19:03:26 -0500542 int ecc_en_flag, transfer_spare_flag;
Chin Liang See3eb3e722014-09-12 00:42:17 -0500543
544 /* set ECC, transfer spare bits if needed */
545 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
546 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
547
548 /* Enable spare area/ECC per user's request. */
549 writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
550 /* applicable for MAP01 only */
551 writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
552}
553
Scott Woodd3963722015-06-26 19:03:26 -0500554/*
555 * sends a pipeline command operation to the controller. See the Denali NAND
Chin Liang See3eb3e722014-09-12 00:42:17 -0500556 * controller's user guide for more information (section 4.2.3.6).
557 */
558static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
Scott Woodd3963722015-06-26 19:03:26 -0500559 bool ecc_en, bool transfer_spare,
560 int access_type, int op)
Chin Liang See3eb3e722014-09-12 00:42:17 -0500561{
562 uint32_t addr, cmd, irq_status;
563 static uint32_t page_count = 1;
564
565 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
566
Chin Liang See3eb3e722014-09-12 00:42:17 -0500567 clear_interrupts(denali);
568
569 addr = BANK(denali->flash_bank) | denali->page;
570
571 /* setup the acccess type */
572 cmd = MODE_10 | addr;
573 index_addr(denali, cmd, access_type);
574
575 /* setup the pipeline command */
576 index_addr(denali, cmd, 0x2000 | op | page_count);
577
578 cmd = MODE_01 | addr;
579 writel(cmd, denali->flash_mem + INDEX_CTRL_REG);
580
581 if (op == DENALI_READ) {
582 /* wait for command to be accepted */
583 irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP);
584
585 if (irq_status == 0)
586 return -EIO;
587 }
588
589 return 0;
590}
591
592/* helper function that simply writes a buffer to the flash */
593static int write_data_to_flash_mem(struct denali_nand_info *denali,
Scott Woodd3963722015-06-26 19:03:26 -0500594 const uint8_t *buf, int len)
Chin Liang See3eb3e722014-09-12 00:42:17 -0500595{
Scott Woodd3963722015-06-26 19:03:26 -0500596 uint32_t *buf32;
597 int i;
Chin Liang See3eb3e722014-09-12 00:42:17 -0500598
Scott Woodd3963722015-06-26 19:03:26 -0500599 /*
600 * verify that the len is a multiple of 4.
601 * see comment in read_data_from_flash_mem()
602 */
Chin Liang See3eb3e722014-09-12 00:42:17 -0500603 BUG_ON((len % 4) != 0);
604
605 /* write the data to the flash memory */
606 buf32 = (uint32_t *)buf;
607 for (i = 0; i < len / 4; i++)
608 writel(*buf32++, denali->flash_mem + INDEX_DATA_REG);
609 return i * 4; /* intent is to return the number of bytes read */
610}
611
612/* helper function that simply reads a buffer from the flash */
613static int read_data_from_flash_mem(struct denali_nand_info *denali,
Scott Woodd3963722015-06-26 19:03:26 -0500614 uint8_t *buf, int len)
Chin Liang See3eb3e722014-09-12 00:42:17 -0500615{
Scott Woodd3963722015-06-26 19:03:26 -0500616 uint32_t *buf32;
617 int i;
Chin Liang See3eb3e722014-09-12 00:42:17 -0500618
619 /*
Scott Woodd3963722015-06-26 19:03:26 -0500620 * we assume that len will be a multiple of 4, if not it would be nice
621 * to know about it ASAP rather than have random failures...
622 * This assumption is based on the fact that this function is designed
623 * to be used to read flash pages, which are typically multiples of 4.
Chin Liang See3eb3e722014-09-12 00:42:17 -0500624 */
Chin Liang See3eb3e722014-09-12 00:42:17 -0500625 BUG_ON((len % 4) != 0);
626
627 /* transfer the data from the flash */
628 buf32 = (uint32_t *)buf;
629 for (i = 0; i < len / 4; i++)
630 *buf32++ = readl(denali->flash_mem + INDEX_DATA_REG);
631
632 return i * 4; /* intent is to return the number of bytes read */
633}
634
635static void denali_mode_main_access(struct denali_nand_info *denali)
636{
637 uint32_t addr, cmd;
638
639 addr = BANK(denali->flash_bank) | denali->page;
640 cmd = MODE_10 | addr;
641 index_addr(denali, cmd, MAIN_ACCESS);
642}
643
644static void denali_mode_main_spare_access(struct denali_nand_info *denali)
645{
646 uint32_t addr, cmd;
647
648 addr = BANK(denali->flash_bank) | denali->page;
649 cmd = MODE_10 | addr;
650 index_addr(denali, cmd, MAIN_SPARE_ACCESS);
651}
652
653/* writes OOB data to the device */
654static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
655{
656 struct denali_nand_info *denali = mtd_to_denali(mtd);
657 uint32_t irq_status;
658 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
659 INTR_STATUS__PROGRAM_FAIL;
660 int status = 0;
661
662 denali->page = page;
663
664 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
665 DENALI_WRITE) == 0) {
666 write_data_to_flash_mem(denali, buf, mtd->oobsize);
667
668 /* wait for operation to complete */
669 irq_status = wait_for_irq(denali, irq_mask);
670
671 if (irq_status == 0) {
672 dev_err(denali->dev, "OOB write failed\n");
673 status = -EIO;
674 }
675 } else {
676 printf("unable to send pipeline command\n");
677 status = -EIO;
678 }
679 return status;
680}
681
682/* reads OOB data from the device */
683static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
684{
685 struct denali_nand_info *denali = mtd_to_denali(mtd);
Scott Woodd3963722015-06-26 19:03:26 -0500686 uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
687 uint32_t irq_status, addr, cmd;
Chin Liang See3eb3e722014-09-12 00:42:17 -0500688
689 denali->page = page;
690
691 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
692 DENALI_READ) == 0) {
693 read_data_from_flash_mem(denali, buf, mtd->oobsize);
694
Scott Woodd3963722015-06-26 19:03:26 -0500695 /*
696 * wait for command to be accepted
697 * can always use status0 bit as the
698 * mask is identical for each bank.
699 */
Chin Liang See3eb3e722014-09-12 00:42:17 -0500700 irq_status = wait_for_irq(denali, irq_mask);
701
702 if (irq_status == 0)
703 printf("page on OOB timeout %d\n", denali->page);
704
Scott Woodd3963722015-06-26 19:03:26 -0500705 /*
706 * We set the device back to MAIN_ACCESS here as I observed
Chin Liang See3eb3e722014-09-12 00:42:17 -0500707 * instability with the controller if you do a block erase
708 * and the last transaction was a SPARE_ACCESS. Block erase
709 * is reliable (according to the MTD test infrastructure)
710 * if you are in MAIN_ACCESS.
711 */
712 addr = BANK(denali->flash_bank) | denali->page;
713 cmd = MODE_10 | addr;
714 index_addr(denali, cmd, MAIN_ACCESS);
715 }
716}
717
Scott Woodd3963722015-06-26 19:03:26 -0500718/*
719 * this function examines buffers to see if they contain data that
Chin Liang See3eb3e722014-09-12 00:42:17 -0500720 * indicate that the buffer is part of an erased region of flash.
721 */
722static bool is_erased(uint8_t *buf, int len)
723{
Scott Woodd3963722015-06-26 19:03:26 -0500724 int i;
725
Chin Liang See3eb3e722014-09-12 00:42:17 -0500726 for (i = 0; i < len; i++)
727 if (buf[i] != 0xFF)
728 return false;
729 return true;
730}
731
732/* programs the controller to either enable/disable DMA transfers */
733static void denali_enable_dma(struct denali_nand_info *denali, bool en)
734{
Scott Woodd3963722015-06-26 19:03:26 -0500735 writel(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
Chin Liang See3eb3e722014-09-12 00:42:17 -0500736 readl(denali->flash_reg + DMA_ENABLE);
737}
738
739/* setups the HW to perform the data DMA */
740static void denali_setup_dma(struct denali_nand_info *denali, int op)
741{
742 uint32_t mode;
743 const int page_count = 1;
744 uint32_t addr = (uint32_t)denali->buf.dma_buf;
745
746 flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));
747
748/* For Denali controller that is 64 bit bus IP core */
749#ifdef CONFIG_SYS_NAND_DENALI_64BIT
750 mode = MODE_10 | BANK(denali->flash_bank) | denali->page;
751
752 /* DMA is a three step process */
753
754 /* 1. setup transfer type, interrupt when complete,
755 burst len = 64 bytes, the number of pages */
756 index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);
757
758 /* 2. set memory low address bits 31:0 */
759 index_addr(denali, mode, addr);
760
761 /* 3. set memory high address bits 64:32 */
762 index_addr(denali, mode, 0);
763#else
764 mode = MODE_10 | BANK(denali->flash_bank);
765
766 /* DMA is a four step process */
767
768 /* 1. setup transfer type and # of pages */
769 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
770
771 /* 2. set memory high address bits 23:8 */
Scott Woodd3963722015-06-26 19:03:26 -0500772 index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
Chin Liang See3eb3e722014-09-12 00:42:17 -0500773
774 /* 3. set memory low address bits 23:8 */
Scott Woodd3963722015-06-26 19:03:26 -0500775 index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
Chin Liang See3eb3e722014-09-12 00:42:17 -0500776
Scott Woodd3963722015-06-26 19:03:26 -0500777 /* 4. interrupt when complete, burst len = 64 bytes */
Chin Liang See3eb3e722014-09-12 00:42:17 -0500778 index_addr(denali, mode | 0x14000, 0x2400);
779#endif
780}
781
782/* Common DMA function */
783static uint32_t denali_dma_configuration(struct denali_nand_info *denali,
784 uint32_t ops, bool raw_xfer,
785 uint32_t irq_mask, int oob_required)
786{
787 uint32_t irq_status = 0;
788 /* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */
789 setup_ecc_for_xfer(denali, !raw_xfer, oob_required);
790
791 /* clear any previous interrupt flags */
792 clear_interrupts(denali);
793
794 /* enable the DMA */
795 denali_enable_dma(denali, true);
796
797 /* setup the DMA */
798 denali_setup_dma(denali, ops);
799
800 /* wait for operation to complete */
801 irq_status = wait_for_irq(denali, irq_mask);
802
803 /* if ECC fault happen, seems we need delay before turning off DMA.
804 * If not, the controller will go into non responsive condition */
805 if (irq_status & INTR_STATUS__ECC_UNCOR_ERR)
806 udelay(100);
807
808 /* disable the DMA */
809 denali_enable_dma(denali, false);
810
811 return irq_status;
812}
813
814static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
815 const uint8_t *buf, bool raw_xfer, int oob_required)
816{
817 struct denali_nand_info *denali = mtd_to_denali(mtd);
818
819 uint32_t irq_status = 0;
820 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
821
822 denali->status = 0;
823
824 /* copy buffer into DMA buffer */
825 memcpy(denali->buf.dma_buf, buf, mtd->writesize);
826
827 /* need extra memcpy for raw transfer */
828 if (raw_xfer)
829 memcpy(denali->buf.dma_buf + mtd->writesize,
830 chip->oob_poi, mtd->oobsize);
831
832 /* setting up DMA */
833 irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer,
834 irq_mask, oob_required);
835
836 /* if timeout happen, error out */
837 if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
838 debug("DMA timeout for denali write_page\n");
839 denali->status = NAND_STATUS_FAIL;
840 return -EIO;
841 }
842
843 if (irq_status & INTR_STATUS__LOCKED_BLK) {
844 debug("Failed as write to locked block\n");
845 denali->status = NAND_STATUS_FAIL;
846 return -EIO;
847 }
848 return 0;
849}
850
851/* NAND core entry points */
852
853/*
854 * this is the callback that the NAND core calls to write a page. Since
855 * writing a page with ECC or without is similar, all the work is done
856 * by write_page above.
857 */
858static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
859 const uint8_t *buf, int oob_required)
860{
861 struct denali_nand_info *denali = mtd_to_denali(mtd);
862
863 /*
864 * for regular page writes, we let HW handle all the ECC
865 * data written to the device.
866 */
867 if (oob_required)
868 /* switch to main + spare access */
869 denali_mode_main_spare_access(denali);
870 else
871 /* switch to main access only */
872 denali_mode_main_access(denali);
873
874 return write_page(mtd, chip, buf, false, oob_required);
875}
876
877/*
878 * This is the callback that the NAND core calls to write a page without ECC.
879 * raw access is similar to ECC page writes, so all the work is done in the
880 * write_page() function above.
881 */
882static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
883 const uint8_t *buf, int oob_required)
884{
885 struct denali_nand_info *denali = mtd_to_denali(mtd);
886
887 /*
888 * for raw page writes, we want to disable ECC and simply write
889 * whatever data is in the buffer.
890 */
891
892 if (oob_required)
893 /* switch to main + spare access */
894 denali_mode_main_spare_access(denali);
895 else
896 /* switch to main access only */
897 denali_mode_main_access(denali);
898
899 return write_page(mtd, chip, buf, true, oob_required);
900}
901
902static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
903 int page)
904{
905 return write_oob_data(mtd, chip->oob_poi, page);
906}
907
908/* raw include ECC value and all the spare area */
909static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
910 uint8_t *buf, int oob_required, int page)
911{
912 struct denali_nand_info *denali = mtd_to_denali(mtd);
913
914 uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
915
916 if (denali->page != page) {
917 debug("Missing NAND_CMD_READ0 command\n");
918 return -EIO;
919 }
920
921 if (oob_required)
922 /* switch to main + spare access */
923 denali_mode_main_spare_access(denali);
924 else
925 /* switch to main access only */
926 denali_mode_main_access(denali);
927
928 /* setting up the DMA where ecc_enable is false */
929 irq_status = denali_dma_configuration(denali, DENALI_READ, true,
930 irq_mask, oob_required);
931
932 /* if timeout happen, error out */
933 if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
934 debug("DMA timeout for denali_read_page_raw\n");
935 return -EIO;
936 }
937
938 /* splitting the content to destination buffer holder */
939 memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize),
940 mtd->oobsize);
941 memcpy(buf, denali->buf.dma_buf, mtd->writesize);
942
943 return 0;
944}
945
946static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
947 uint8_t *buf, int oob_required, int page)
948{
949 struct denali_nand_info *denali = mtd_to_denali(mtd);
950 uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
951
952 if (denali->page != page) {
953 debug("Missing NAND_CMD_READ0 command\n");
954 return -EIO;
955 }
956
957 if (oob_required)
958 /* switch to main + spare access */
959 denali_mode_main_spare_access(denali);
960 else
961 /* switch to main access only */
962 denali_mode_main_access(denali);
963
964 /* setting up the DMA where ecc_enable is true */
965 irq_status = denali_dma_configuration(denali, DENALI_READ, false,
966 irq_mask, oob_required);
967
968 memcpy(buf, denali->buf.dma_buf, mtd->writesize);
969
970 /* check whether any ECC error */
971 if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) {
972 /* is the ECC cause by erase page, check using read_page_raw */
973 debug(" Uncorrected ECC detected\n");
974 denali_read_page_raw(mtd, chip, buf, oob_required,
975 denali->page);
976
977 if (is_erased(buf, mtd->writesize) == true &&
978 is_erased(chip->oob_poi, mtd->oobsize) == true) {
979 debug(" ECC error cause by erased block\n");
980 /* false alarm, return the 0xFF */
981 } else {
982 return -EIO;
983 }
984 }
985 memcpy(buf, denali->buf.dma_buf, mtd->writesize);
986 return 0;
987}
988
989static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
990 int page)
991{
992 read_oob_data(mtd, chip->oob_poi, page);
993
994 return 0;
995}
996
997static uint8_t denali_read_byte(struct mtd_info *mtd)
998{
999 struct denali_nand_info *denali = mtd_to_denali(mtd);
1000 uint32_t addr, result;
1001
1002 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1003 index_addr_read_data(denali, addr | 2, &result);
1004 return (uint8_t)result & 0xFF;
1005}
1006
1007static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1008{
1009 struct denali_nand_info *denali = mtd_to_denali(mtd);
1010 uint32_t i, addr, result;
1011
1012 /* delay for tR (data transfer from Flash array to data register) */
1013 udelay(25);
1014
1015 /* ensure device completed else additional delay and polling */
1016 wait_for_irq(denali, INTR_STATUS__INT_ACT);
1017
1018 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1019 for (i = 0; i < len; i++) {
1020 index_addr_read_data(denali, (uint32_t)addr | 2, &result);
1021 write_byte_to_buf(denali, result);
1022 }
1023 memcpy(buf, denali->buf.buf, len);
1024}
1025
1026static void denali_select_chip(struct mtd_info *mtd, int chip)
1027{
1028 struct denali_nand_info *denali = mtd_to_denali(mtd);
1029
1030 denali->flash_bank = chip;
1031}
1032
1033static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1034{
1035 struct denali_nand_info *denali = mtd_to_denali(mtd);
1036 int status = denali->status;
Scott Woodd3963722015-06-26 19:03:26 -05001037
Chin Liang See3eb3e722014-09-12 00:42:17 -05001038 denali->status = 0;
1039
1040 return status;
1041}
1042
Scott Woodd3963722015-06-26 19:03:26 -05001043static int denali_erase(struct mtd_info *mtd, int page)
Chin Liang See3eb3e722014-09-12 00:42:17 -05001044{
1045 struct denali_nand_info *denali = mtd_to_denali(mtd);
Scott Woodd3963722015-06-26 19:03:26 -05001046
Chin Liang See3eb3e722014-09-12 00:42:17 -05001047 uint32_t cmd, irq_status;
1048
Chin Liang See3eb3e722014-09-12 00:42:17 -05001049 clear_interrupts(denali);
1050
1051 /* setup page read request for access type */
1052 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1053 index_addr(denali, cmd, 0x1);
1054
1055 /* wait for erase to complete or failure to occur */
1056 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1057 INTR_STATUS__ERASE_FAIL);
1058
1059 if (irq_status & INTR_STATUS__ERASE_FAIL ||
1060 irq_status & INTR_STATUS__LOCKED_BLK)
Scott Woodd3963722015-06-26 19:03:26 -05001061 return NAND_STATUS_FAIL;
1062
1063 return 0;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001064}
1065
1066static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1067 int page)
1068{
1069 struct denali_nand_info *denali = mtd_to_denali(mtd);
1070 uint32_t addr;
1071
1072 switch (cmd) {
1073 case NAND_CMD_PAGEPROG:
1074 break;
1075 case NAND_CMD_STATUS:
1076 addr = MODE_11 | BANK(denali->flash_bank);
1077 index_addr(denali, addr | 0, cmd);
1078 break;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001079 case NAND_CMD_READID:
Masahiro Yamada05968e72014-10-03 20:03:03 +09001080 case NAND_CMD_PARAM:
Chin Liang See3eb3e722014-09-12 00:42:17 -05001081 reset_buf(denali);
Scott Woodd3963722015-06-26 19:03:26 -05001082 /*
1083 * sometimes ManufactureId read from register is not right
Chin Liang See3eb3e722014-09-12 00:42:17 -05001084 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1085 * So here we send READID cmd to NAND insteand
Scott Woodd3963722015-06-26 19:03:26 -05001086 */
Chin Liang See3eb3e722014-09-12 00:42:17 -05001087 addr = MODE_11 | BANK(denali->flash_bank);
1088 index_addr(denali, addr | 0, cmd);
1089 index_addr(denali, addr | 1, col & 0xFF);
Masahiro Yamada05968e72014-10-03 20:03:03 +09001090 if (cmd == NAND_CMD_PARAM)
1091 udelay(50);
Chin Liang See3eb3e722014-09-12 00:42:17 -05001092 break;
Masahiro Yamadaed3c9802014-10-03 20:03:04 +09001093 case NAND_CMD_RNDOUT:
1094 addr = MODE_11 | BANK(denali->flash_bank);
1095 index_addr(denali, addr | 0, cmd);
1096 index_addr(denali, addr | 1, col & 0xFF);
1097 index_addr(denali, addr | 1, col >> 8);
1098 index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART);
1099 break;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001100 case NAND_CMD_READ0:
1101 case NAND_CMD_SEQIN:
1102 denali->page = page;
1103 break;
1104 case NAND_CMD_RESET:
1105 reset_bank(denali);
1106 break;
1107 case NAND_CMD_READOOB:
1108 /* TODO: Read OOB data */
1109 break;
1110 case NAND_CMD_ERASE1:
1111 /*
1112 * supporting block erase only, not multiblock erase as
1113 * it will cross plane and software need complex calculation
1114 * to identify the block count for the cross plane
1115 */
1116 denali_erase(mtd, page);
1117 break;
1118 case NAND_CMD_ERASE2:
1119 /* nothing to do here as it was done during NAND_CMD_ERASE1 */
1120 break;
1121 case NAND_CMD_UNLOCK1:
1122 addr = MODE_10 | BANK(denali->flash_bank) | page;
1123 index_addr(denali, addr | 0, DENALI_UNLOCK_START);
1124 break;
1125 case NAND_CMD_UNLOCK2:
1126 addr = MODE_10 | BANK(denali->flash_bank) | page;
1127 index_addr(denali, addr | 0, DENALI_UNLOCK_END);
1128 break;
1129 case NAND_CMD_LOCK:
1130 addr = MODE_10 | BANK(denali->flash_bank);
1131 index_addr(denali, addr | 0, DENALI_LOCK);
1132 break;
1133 default:
1134 printf(": unsupported command received 0x%x\n", cmd);
1135 break;
1136 }
1137}
1138/* end NAND core entry points */
1139
1140/* Initialization code to bring the device up to a known good state */
1141static void denali_hw_init(struct denali_nand_info *denali)
1142{
1143 /*
1144 * tell driver how many bit controller will skip before writing
1145 * ECC code in OOB. This is normally used for bad block marker
1146 */
1147 writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
1148 denali->flash_reg + SPARE_AREA_SKIP_BYTES);
1149 detect_max_banks(denali);
1150 denali_nand_reset(denali);
1151 writel(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1152 writel(CHIP_EN_DONT_CARE__FLAG,
1153 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1154 writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1155
1156 /* Should set value for these registers when init */
1157 writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1158 writel(1, denali->flash_reg + ECC_ENABLE);
1159 denali_nand_timing_set(denali);
1160 denali_irq_init(denali);
1161}
1162
1163static struct nand_ecclayout nand_oob;
1164
Masahiro Yamada65e41452014-11-13 20:31:50 +09001165static int denali_init(struct denali_nand_info *denali)
Chin Liang See3eb3e722014-09-12 00:42:17 -05001166{
Masahiro Yamada65e41452014-11-13 20:31:50 +09001167 int ret;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001168
Masahiro Yamada65e41452014-11-13 20:31:50 +09001169 denali_hw_init(denali);
Chin Liang See3eb3e722014-09-12 00:42:17 -05001170
Masahiro Yamada65e41452014-11-13 20:31:50 +09001171 denali->mtd->name = "denali-nand";
1172 denali->mtd->owner = THIS_MODULE;
1173 denali->mtd->priv = &denali->nand;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001174
Masahiro Yamada65e41452014-11-13 20:31:50 +09001175 /* register the driver with the NAND core subsystem */
1176 denali->nand.select_chip = denali_select_chip;
1177 denali->nand.cmdfunc = denali_cmdfunc;
1178 denali->nand.read_byte = denali_read_byte;
1179 denali->nand.read_buf = denali_read_buf;
1180 denali->nand.waitfunc = denali_waitfunc;
1181
1182 /*
1183 * scan for NAND devices attached to the controller
1184 * this is the first stage in a two step process to register
1185 * with the nand subsystem
1186 */
1187 if (nand_scan_ident(denali->mtd, denali->max_banks, NULL)) {
1188 ret = -ENXIO;
1189 goto fail;
1190 }
Chin Liang See3eb3e722014-09-12 00:42:17 -05001191
1192#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1193 /* check whether flash got BBT table (located at end of flash). As we
1194 * use NAND_BBT_NO_OOB, the BBT page will start with
1195 * bbt_pattern. We will have mirror pattern too */
Masahiro Yamada65e41452014-11-13 20:31:50 +09001196 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001197 /*
1198 * We are using main + spare with ECC support. As BBT need ECC support,
1199 * we need to ensure BBT code don't write to OOB for the BBT pattern.
1200 * All BBT info will be stored into data area with ECC support.
1201 */
Masahiro Yamada65e41452014-11-13 20:31:50 +09001202 denali->nand.bbt_options |= NAND_BBT_NO_OOB;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001203#endif
1204
Masahiro Yamada65e41452014-11-13 20:31:50 +09001205 denali->nand.ecc.mode = NAND_ECC_HW;
1206 denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
1207
Scott Woodd3963722015-06-26 19:03:26 -05001208 /* no subpage writes on denali */
1209 denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
1210
Chin Liang See3eb3e722014-09-12 00:42:17 -05001211 /*
1212 * Tell driver the ecc strength. This register may be already set
1213 * correctly. So we read this value out.
1214 */
Masahiro Yamada65e41452014-11-13 20:31:50 +09001215 denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
1216 switch (denali->nand.ecc.size) {
Chin Liang See3eb3e722014-09-12 00:42:17 -05001217 case 512:
Masahiro Yamada65e41452014-11-13 20:31:50 +09001218 denali->nand.ecc.bytes =
1219 (denali->nand.ecc.strength * 13 + 15) / 16 * 2;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001220 break;
1221 case 1024:
Masahiro Yamada65e41452014-11-13 20:31:50 +09001222 denali->nand.ecc.bytes =
1223 (denali->nand.ecc.strength * 14 + 15) / 16 * 2;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001224 break;
1225 default:
1226 pr_err("Unsupported ECC size\n");
Masahiro Yamada65e41452014-11-13 20:31:50 +09001227 ret = -EINVAL;
1228 goto fail;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001229 }
Masahiro Yamada65e41452014-11-13 20:31:50 +09001230 nand_oob.eccbytes = denali->nand.ecc.bytes;
1231 denali->nand.ecc.layout = &nand_oob;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001232
Masahiro Yamadaf09eb522014-11-13 20:31:51 +09001233 writel(denali->mtd->erasesize / denali->mtd->writesize,
1234 denali->flash_reg + PAGES_PER_BLOCK);
1235 writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0,
1236 denali->flash_reg + DEVICE_WIDTH);
1237 writel(denali->mtd->writesize,
1238 denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
1239 writel(denali->mtd->oobsize,
1240 denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
1241 if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0)
1242 writel(1, denali->flash_reg + DEVICES_CONNECTED);
1243
Masahiro Yamada65e41452014-11-13 20:31:50 +09001244 /* override the default operations */
1245 denali->nand.ecc.read_page = denali_read_page;
1246 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1247 denali->nand.ecc.write_page = denali_write_page;
1248 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1249 denali->nand.ecc.read_oob = denali_read_oob;
1250 denali->nand.ecc.write_oob = denali_write_oob;
1251
1252 if (nand_scan_tail(denali->mtd)) {
1253 ret = -ENXIO;
1254 goto fail;
1255 }
1256
1257 ret = nand_register(0);
1258
1259fail:
1260 return ret;
Chin Liang See3eb3e722014-09-12 00:42:17 -05001261}
1262
Masahiro Yamada65e41452014-11-13 20:31:50 +09001263static int __board_nand_init(void)
Chin Liang See3eb3e722014-09-12 00:42:17 -05001264{
Masahiro Yamada65e41452014-11-13 20:31:50 +09001265 struct denali_nand_info *denali;
1266
1267 denali = kzalloc(sizeof(*denali), GFP_KERNEL);
1268 if (!denali)
1269 return -ENOMEM;
1270
1271 /*
1272 * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible
1273 * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c
1274 * still provides a "struct mtd_info nand_info" instance.
1275 */
1276 denali->mtd = &nand_info[0];
1277
1278 /*
1279 * In the future, these base addresses should be taken from
1280 * Device Tree or platform data.
1281 */
1282 denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
1283 denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
1284
1285 return denali_init(denali);
1286}
1287
1288void board_nand_init(void)
1289{
1290 if (__board_nand_init() < 0)
1291 pr_warn("Failed to initialize Denali NAND controller.\n");
Chin Liang See3eb3e722014-09-12 00:42:17 -05001292}