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Wolfgang Denkba94a1b2006-05-30 15:56:48 +02001/*
Stefan Roese1bbf5ea2007-01-30 15:01:49 +01002 * (C) Copyright 2006-2007
Wolfgang Denkba94a1b2006-05-30 15:56:48 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Configuation settings for the PDNB3 board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
33#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
34#define CONFIG_PDNB3 1 /* on an PDNB3 board */
35
36#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
37#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
38
39/*
40 * Ethernet
41 */
42#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
43#define CONFIG_NET_MULTI 1
44#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */
45#define CONFIG_HAS_ETH1
46#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */
47#define CONFIG_MII 1 /* MII PHY management */
48#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
49
50/*
51 * Misc configuration options
52 */
53#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
54
55#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
56#define CFG_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
57
58#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
59#define CONFIG_SETUP_MEMORY_TAGS 1
60#define CONFIG_INITRD_TAG 1
61
62/*
63 * Size of malloc() pool
64 */
65#define CFG_MALLOC_LEN (1 << 20)
66#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
67
68/* allow to overwrite serial and ethaddr */
69#define CONFIG_ENV_OVERWRITE
70
71#define CONFIG_BAUDRATE 115200
72#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
73
Jon Loeliger26a34562007-07-04 22:33:17 -050074
75/*
Jon Loeliger079a1362007-07-10 10:12:10 -050076 * BOOTP options
77 */
78#define CONFIG_BOOTP_BOOTFILESIZE
79#define CONFIG_BOOTP_BOOTPATH
80#define CONFIG_BOOTP_GATEWAY
81#define CONFIG_BOOTP_HOSTNAME
82
83
84/*
Jon Loeliger26a34562007-07-04 22:33:17 -050085 * Command line configuration.
86 */
87#include <config_cmd_default.h>
88
89#define CONFIG_CMD_DHCP
90#define CONFIG_CMD_DATE
91#define CONFIG_CMD_NET
92#define CONFIG_CMD_MII
93#define CONFIG_CMD_I2C
94#define CONFIG_CMD_ELF
95#define CONFIG_CMD_PING
96
97#if !defined(CONFIG_SCPU)
98#define CONFIG_CMD_NAND
Stefan Roese9d8d5a52007-01-18 16:05:47 +010099#endif
100
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200101
102#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
103#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
104
105/*
106 * Miscellaneous configurable options
107 */
108#define CFG_LONGHELP /* undef to save memory */
109#define CFG_PROMPT "=> " /* Monitor Command Prompt */
110#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
111#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
112#define CFG_MAXARGS 16 /* max number of command args */
113#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
114
115#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
116#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
117#define CFG_LOAD_ADDR 0x00010000 /* default load address */
118
119#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
120#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
121 /* valid baudrates */
122#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
123
124/*
125 * Stack sizes
126 *
127 * The stack sizes are set up in start.S using the settings below
128 */
129#define CONFIG_STACKSIZE (128*1024) /* regular stack */
130#ifdef CONFIG_USE_IRQ
131#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
132#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
133#endif
134
135/***************************************************************
136 * Platform/Board specific defines start here.
137 ***************************************************************/
138
139/*-----------------------------------------------------------------------
140 * Default configuration (environment varibles...)
141 *----------------------------------------------------------------------*/
142#define CONFIG_PREBOOT "echo;" \
143 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
144 "echo"
145
146#undef CONFIG_BOOTARGS
147
148#define CONFIG_EXTRA_ENV_SETTINGS \
149 "netdev=eth0\0" \
150 "hostname=pdnb3\0" \
151 "nfsargs=setenv bootargs root=/dev/nfs rw " \
152 "nfsroot=${serverip}:${rootpath}\0" \
153 "ramargs=setenv bootargs root=/dev/ram rw\0" \
154 "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
155 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
156 ":${hostname}:${netdev}:off panic=1\0" \
157 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
158 "mtdparts=${mtdparts}\0" \
159 "flash_nfs=run nfsargs addip addtty;" \
160 "bootm ${kernel_addr}\0" \
161 "flash_self=run ramargs addip addtty;" \
162 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
163 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
164 "bootm\0" \
165 "rootpath=/opt/buildroot\0" \
166 "bootfile=/tftpboot/netbox/uImage\0" \
167 "kernel_addr=50080000\0" \
168 "ramdisk_addr=50200000\0" \
169 "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
170 "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
171 "cp.b 100000 50000000 ${filesize};" \
172 "setenv filesize;saveenv\0" \
173 "upd=run load;run update\0" \
174 "ipaddr=10.0.0.233\0" \
175 "serverip=10.0.0.152\0" \
176 "netmask=255.255.0.0\0" \
177 "ethaddr=c6:6f:13:36:f3:81\0" \
178 "eth1addr=c6:6f:13:36:f3:82\0" \
179 "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
180 "4k@508k(renv)\0" \
181 ""
182#define CONFIG_BOOTCOMMAND "run net_nfs"
183
184/*
185 * Physical Memory Map
186 */
187#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
188#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
189#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
190
191#define CFG_FLASH_BASE 0x50000000
192#define CFG_MONITOR_BASE CFG_FLASH_BASE
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100193#if defined(CONFIG_SCPU)
194#define CFG_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */
195#else
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200196#define CFG_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100197#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200198
199/*
200 * Expansion bus settings
201 */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100202#if defined(CONFIG_SCPU)
203#define CFG_EXP_CS0 0x94d23C42 /* 8bit, max size */
204#else
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200205#define CFG_EXP_CS0 0x94913C43 /* 8bit, max size */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100206#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200207#define CFG_EXP_CS1 0x85000043 /* 8bit, 512bytes */
208
209/*
210 * SDRAM settings
211 */
212#define CFG_SDR_CONFIG 0x18
213#define CFG_SDR_MODE_CONFIG 0x1
214#define CFG_SDRAM_REFRESH_CNT 0x81a
215
216/*
217 * FLASH and environment organization
218 */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100219#if defined(CONFIG_SCPU)
220#define CFG_FLASH_CFI /* The flash is CFI compatible */
221#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
222#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
223#endif
224
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200225#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
226
227#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
228#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
229
230#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
231#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
232
233#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
234#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
235#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
236/*
237 * The following defines are added for buggy IOP480 byte interface.
238 * All other boards should use the standard values (CPCI405 etc.)
239 */
240#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
241#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
242#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
243
244#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
245
246#define CFG_ENV_IS_IN_FLASH 1
247
Stefan Roese1bbf5ea2007-01-30 15:01:49 +0100248#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100249#if defined(CONFIG_SCPU)
Stefan Roese1bbf5ea2007-01-30 15:01:49 +0100250/* no redundant environment on SCPU */
251#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100252#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
253#else
Stefan Roese1bbf5ea2007-01-30 15:01:49 +0100254#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200255#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
256
257/* Address and size of Redundant Environment Sector */
258#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
259#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
Stefan Roese1bbf5ea2007-01-30 15:01:49 +0100260#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200261
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100262#if !defined(CONFIG_SCPU)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200263/*
264 * NAND-FLASH stuff
265 */
266#define CFG_MAX_NAND_DEVICE 1
267#define NAND_MAX_CHIPS 1
268#define CFG_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100269#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200270
271/*
272 * GPIO settings
273 */
274
275/* FPGA program pin configuration */
276#define CFG_GPIO_PRG 12 /* FPGA program pin (cpu output)*/
277#define CFG_GPIO_CLK 10 /* FPGA clk pin (cpu output) */
278#define CFG_GPIO_DATA 14 /* FPGA data pin (cpu output) */
279#define CFG_GPIO_INIT 13 /* FPGA init pin (cpu input) */
280#define CFG_GPIO_DONE 11 /* FPGA done pin (cpu input) */
281
282/* other GPIO's */
283#define CFG_GPIO_RESTORE_INT 0
284#define CFG_GPIO_RESTART_INT 1
285#define CFG_GPIO_SYS_RUNNING 2
286#define CFG_GPIO_PCI_INTA 3
287#define CFG_GPIO_PCI_INTB 4
288#define CFG_GPIO_I2C_SCL 6
289#define CFG_GPIO_I2C_SDA 7
290#define CFG_GPIO_FPGA_RESET 9
291#define CFG_GPIO_CLK_33M 15
292
293/*
294 * I2C stuff
295 */
296
297/* enable I2C and select the hardware/software driver */
298#undef CONFIG_HARD_I2C /* I2C with hardware support */
299#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
300
301#define CFG_I2C_SPEED 83000 /* 83 kHz is supposed to work */
302#define CFG_I2C_SLAVE 0xFE
303
304/*
305 * Software (bit-bang) I2C driver configuration
306 */
307#define PB_SCL (1 << CFG_GPIO_I2C_SCL)
308#define PB_SDA (1 << CFG_GPIO_I2C_SDA)
309
310#define I2C_INIT GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SCL)
311#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SDA)
312#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CFG_GPIO_I2C_SDA)
313#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
314#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SDA); \
315 else GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SDA)
316#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SCL); \
317 else GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SCL)
318#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
319
320/*
321 * I2C RTC
322 */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100323#if 0 /* test-only */
324#define CONFIG_RTC_DS1340 1
325#define CFG_I2C_RTC_ADDR 0x68
326#else
327/* M41T11 Serial Access Timekeeper(R) SRAM */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200328#define CONFIG_RTC_M41T11 1
329#define CFG_I2C_RTC_ADDR 0x68
330#define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100331#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200332
333/*
334 * Spartan3 FPGA configuration support
335 */
336#define CFG_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */
337
338#define CFG_FPGA_PRG (1 << CFG_GPIO_PRG) /* FPGA program pin (cpu output)*/
339#define CFG_FPGA_CLK (1 << CFG_GPIO_CLK) /* FPGA clk pin (cpu output) */
340#define CFG_FPGA_DATA (1 << CFG_GPIO_DATA) /* FPGA data pin (cpu output) */
341#define CFG_FPGA_INIT (1 << CFG_GPIO_INIT) /* FPGA init pin (cpu input) */
342#define CFG_FPGA_DONE (1 << CFG_GPIO_DONE) /* FPGA done pin (cpu input) */
343
344/*
345 * Cache Configuration
346 */
347#define CFG_CACHELINE_SIZE 32
348
349#endif /* __CONFIG_H */