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wdenk2262cfe2002-11-18 00:14:45 +00001/*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_X86 1 /* This is a X86 CPU */
wdenk7a8e9bed2003-05-31 18:35:21 +000037#define CONFIG_SC520 1 /* Include support for AMD SC520 */
38#define CONFIG_ALI152X 1 /* Include support for Ali 152x SIO */
wdenk2262cfe2002-11-18 00:14:45 +000039
wdenk8bde7f72003-06-27 21:31:46 +000040#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */
wdenk2262cfe2002-11-18 00:14:45 +000041#define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
42#define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */
43
44/* define at most one of these */
45#undef CFG_SDRAM_CAS_LATENCY_2T
46#define CFG_SDRAM_CAS_LATENCY_3T
47
48#define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
49#define CFG_RESET_GENERIC 1 /* use tripple-fault to reset cpu */
50#undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */
51#undef CFG_TIMER_SC520 /* use SC520 swtimers */
52#define CFG_TIMER_GENERIC 1 /* use the i8254 PIT timers */
53#undef CFG_TIMER_TSC /* use the Pentium TSC timers */
54#define CFG_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
55 * in the SC520 on the CDP */
56
57#define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */
58
59#define CONFIG_SHOW_BOOT_PROGRESS 1
60#define CONFIG_LAST_STAGE_INIT 1
61
62/*
63 * Size of malloc() pool
64 */
65#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
66
wdenk2262cfe2002-11-18 00:14:45 +000067#define CONFIG_BAUDRATE 9600
68
Jon Loeliger46da1e92007-07-04 22:33:30 -050069/*
Jon Loeliger079a1362007-07-10 10:12:10 -050070 * BOOTP options
71 */
72#define CONFIG_BOOTP_BOOTFILESIZE
73#define CONFIG_BOOTP_BOOTPATH
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76
77
78/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050079 * Command line configuration.
80 */
81#include <config_cmd_default.h>
82
83#define CONFIG_CMD_PCI
84#define CONFIG_CMD_JFFS2
85#define CONFIG_CMD_IDE
86#define CONFIG_CMD_NET
87#define CONFIG_CMD_EEPROM
88
wdenk2262cfe2002-11-18 00:14:45 +000089#define CONFIG_BOOTDELAY 15
90#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
91/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
92
Jon Loeliger46da1e92007-07-04 22:33:30 -050093#if defined(CONFIG_CMD_KGDB)
wdenk2262cfe2002-11-18 00:14:45 +000094#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
95#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
96#endif
97
wdenk2262cfe2002-11-18 00:14:45 +000098/*
99 * Miscellaneous configurable options
100 */
101#define CFG_LONGHELP /* undef to save memory */
102#define CFG_PROMPT "boot > " /* Monitor Command Prompt */
103#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
104#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
105#define CFG_MAXARGS 16 /* max number of command args */
106#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
107
108#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
109#define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
110
111#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
112
wdenk7a8e9bed2003-05-31 18:35:21 +0000113#define CFG_LOAD_ADDR 0x100000 /* default load address */
wdenk2262cfe2002-11-18 00:14:45 +0000114
115#define CFG_HZ 1024 /* incrementer freq: 1kHz */
116
117 /* valid baudrates */
118#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
119
wdenk2262cfe2002-11-18 00:14:45 +0000120/*-----------------------------------------------------------------------
121 * Physical Memory Map
122 */
123#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */
124
wdenk2262cfe2002-11-18 00:14:45 +0000125/*-----------------------------------------------------------------------
126 * FLASH and environment organization
127 */
wdenk7a8e9bed2003-05-31 18:35:21 +0000128#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
wdenk2262cfe2002-11-18 00:14:45 +0000129#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
130
131/* timeout values are in ticks */
132#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
133#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
134
wdenk7a8e9bed2003-05-31 18:35:21 +0000135#define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */
wdenk8bde7f72003-06-27 21:31:46 +0000136#define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */
wdenk2262cfe2002-11-18 00:14:45 +0000137
wdenk7a8e9bed2003-05-31 18:35:21 +0000138/* allow to overwrite serial and ethaddr */
139#define CONFIG_ENV_OVERWRITE
140
wdenk7a8e9bed2003-05-31 18:35:21 +0000141/* Environment in EEPROM */
142#define CFG_ENV_IS_IN_EEPROM 1
143#define CONFIG_SPI
144#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/
wdenk8bde7f72003-06-27 21:31:46 +0000145#define CFG_ENV_OFFSET 0
wdenk7a8e9bed2003-05-31 18:35:21 +0000146#define CONFIG_SC520_CDP_USE_SPI /* Store configuration in the SPI part */
147#undef CONFIG_SC520_CDP_USE_MW /* Store configuration in the MicroWire part */
148#define CONFIG_SPI_X 1
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200149
150/*
151 * JFFS2 partitions
152 */
153/* No command line, one static partition, whole device */
154#undef CONFIG_JFFS2_CMDLINE
155#define CONFIG_JFFS2_DEV "nor0"
156#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
157#define CONFIG_JFFS2_PART_OFFSET 0x00000000
158
159/* mtdparts command line support */
160/*
161#define CONFIG_JFFS2_CMDLINE
162#define MTDIDS_DEFAULT "nor0=SC520CDP Flash Bank #0"
163#define MTDPARTS_DEFAULT "mtdparts=SC520CDP Flash Bank #0:-(jffs2)"
164*/
wdenk7a8e9bed2003-05-31 18:35:21 +0000165
wdenk2262cfe2002-11-18 00:14:45 +0000166/*-----------------------------------------------------------------------
167 * Device drivers
168 */
169#define CONFIG_NET_MULTI /* Multi ethernet cards support */
170#define CONFIG_PCNET
171#define CONFIG_PCNET_79C973
172#define CONFIG_PCNET_79C975
173#define PCNET_HAS_PROM 1
wdenk7a8e9bed2003-05-31 18:35:21 +0000174
wdenk2262cfe2002-11-18 00:14:45 +0000175/************************************************************
176 * IDE/ATA stuff
177 ************************************************************/
wdenk7a8e9bed2003-05-31 18:35:21 +0000178#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
wdenk2262cfe2002-11-18 00:14:45 +0000179#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
180
181#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
wdenk8bde7f72003-06-27 21:31:46 +0000182/*#define CFG_ATA_IDE1_OFFSET 0x0170 /###* ide1 offset */
wdenk2262cfe2002-11-18 00:14:45 +0000183#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
184#define CFG_ATA_REG_OFFSET 0 /* reg offset */
185#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenk7a8e9bed2003-05-31 18:35:21 +0000186#define CFG_ATA_BASE_ADDR 0
wdenk2262cfe2002-11-18 00:14:45 +0000187
wdenk2262cfe2002-11-18 00:14:45 +0000188#undef CONFIG_IDE_LED /* no led for ide supported */
189#undef CONFIG_IDE_RESET /* reset for ide unsupported... */
190#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */
191
192/************************************************************
mushtaq khan66d9dbe2007-04-20 14:23:02 +0530193*SATA/Native Stuff
194************************************************************/
195#define CFG_SATA_SUPPORTED 1
196#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */
197#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */
198#define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
199#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */
200
201/************************************************************
wdenk2262cfe2002-11-18 00:14:45 +0000202 * ATAPI support (experimental)
203 ************************************************************/
204#define CONFIG_ATAPI /* enable ATAPI Support */
205
206/************************************************************
207 * DISK Partition support
208 ************************************************************/
209#define CONFIG_DOS_PARTITION
210#define CONFIG_MAC_PARTITION
211#define CONFIG_ISO_PARTITION /* Experimental */
212
213/************************************************************
wdenk7a8e9bed2003-05-31 18:35:21 +0000214 * Video/Keyboard support
wdenk2262cfe2002-11-18 00:14:45 +0000215 ************************************************************/
wdenk7a8e9bed2003-05-31 18:35:21 +0000216#define CONFIG_VIDEO /* To enable video controller support */
217#define CONFIG_I8042_KBD
218#define CFG_ISA_IO 0
wdenk2262cfe2002-11-18 00:14:45 +0000219
wdenk2262cfe2002-11-18 00:14:45 +0000220/************************************************************
221 * RTC
222 ***********************************************************/
223#define CONFIG_RTC_MC146818
224#undef CONFIG_WATCHDOG /* watchdog disabled */
225
226/*
227 * PCI stuff
228 */
229#define CONFIG_PCI /* include pci support */
230#define CONFIG_PCI_PNP /* pci plug-and-play */
231#define CONFIG_PCI_SCAN_SHOW
232
wdenk7a8e9bed2003-05-31 18:35:21 +0000233#define CFG_FIRST_PCI_IRQ 10
wdenk8bde7f72003-06-27 21:31:46 +0000234#define CFG_SECOND_PCI_IRQ 9
235#define CFG_THIRD_PCI_IRQ 11
wdenk7a8e9bed2003-05-31 18:35:21 +0000236#define CFG_FORTH_PCI_IRQ 15
237
wdenk2262cfe2002-11-18 00:14:45 +0000238#endif /* __CONFIG_H */