blob: 112806c342b7de5936e510a0984ce6a273f33c5b [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +03002/*
3 * include/configs/silk.h
4 * This file is silk board configuration.
5 *
6 * Copyright (C) 2015 Renesas Electronics Corporation
7 * Copyright (C) 2015 Cogent Embedded, Inc.
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +03008 */
9
10#ifndef __SILK_H
11#define __SILK_H
12
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +030013#include "rcar-gen2-common.h"
14
Marek Vasutf7aa3cd2018-04-21 16:19:56 +020015#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
16#define STACK_AREA_SIZE 0x00100000
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +030017#define LOW_LEVEL_MERAM_STACK \
18 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
19
20/* MEMORY */
21#define RCAR_GEN2_SDRAM_BASE 0x40000000
22#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
23#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
24
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +030025/* FLASH */
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +030026#define CONFIG_SPI_FLASH_QUAD
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +030027
28/* SH Ether */
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +030029#define CONFIG_SH_ETHER_USE_PORT 0
30#define CONFIG_SH_ETHER_PHY_ADDR 0x1
31#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
32#define CONFIG_SH_ETHER_CACHE_WRITEBACK
33#define CONFIG_SH_ETHER_CACHE_INVALIDATE
34#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +030035#define CONFIG_BITBANGMII
36#define CONFIG_BITBANGMII_MULTI
37
38/* Board Clock */
39#define RMOBILE_XTAL_CLK 20000000u
40#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +030041
Marek Vasutf7aa3cd2018-04-21 16:19:56 +020042#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut07a80602018-11-27 00:19:03 +010043 "bootm_size=0x10000000\0"
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +030044
Marek Vasutf7aa3cd2018-04-21 16:19:56 +020045/* SPL support */
46#define CONFIG_SPL_TEXT_BASE 0xe6300000
47#define CONFIG_SPL_STACK 0xe6340000
48#define CONFIG_SPL_MAX_SIZE 0x4000
49#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
50#ifdef CONFIG_SPL_BUILD
51#define CONFIG_CONS_SCIF2
52#define CONFIG_SH_SCIF_CLK_FREQ 65000000
53#endif
Vladimir Barinov3b7f0e12015-01-12 19:17:07 +030054
55#endif /* __SILK_H */