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Kumar Gala6a8e5692008-08-26 15:01:35 -05001/*
York Sun712cf7a2011-10-03 09:19:53 -07002 * Copyright 2008,2011 Freescale Semiconductor, Inc.
Kumar Gala6a8e5692008-08-26 15:01:35 -05003 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
Kumar Gala6a8e5692008-08-26 15:01:35 -050010
York Sun5614e712013-09-30 09:22:09 -070011#include <fsl_ddr_sdram.h>
12#include <fsl_ddr_dimm_params.h>
Kumar Gala6a8e5692008-08-26 15:01:35 -050013
York Sun712cf7a2011-10-03 09:19:53 -070014struct board_specific_parameters {
Wolfgang Denk3cbd8232008-11-02 16:14:22 +010015 u32 n_ranks;
York Sun712cf7a2011-10-03 09:19:53 -070016 u32 datarate_mhz_high;
Wolfgang Denk3cbd8232008-11-02 16:14:22 +010017 u32 clk_adjust;
18 u32 cpo;
19 u32 write_data_delay;
York Sun712cf7a2011-10-03 09:19:53 -070020};
Haiying Wangc21617f2008-10-03 12:37:57 -040021
York Sun712cf7a2011-10-03 09:19:53 -070022/*
23 * This table contains all valid speeds we want to override with board
24 * specific parameters. datarate_mhz_high values need to be in ascending order
25 * for each n_ranks group.
26 */
27const struct board_specific_parameters dimm0[] = {
28 /*
29 * memory controller 0
30 * num| hi| clk| cpo|wrdata|2T
31 * ranks| mhz|adjst| | delay|
32 */
33 {4, 333, 7, 7, 3},
34 {4, 549, 7, 9, 3},
35 {4, 650, 7, 10, 4},
36 {2, 333, 7, 7, 3},
37 {2, 549, 7, 9, 3},
38 {2, 650, 7, 10, 4},
39 {1, 333, 7, 7, 3},
40 {1, 549, 7, 9, 3},
41 {1, 650, 7, 10, 4},
42 {}
43};
Haiying Wangc21617f2008-10-03 12:37:57 -040044
York Sun712cf7a2011-10-03 09:19:53 -070045/*
46 * The two slots have slightly different timing. The center values are good
47 * for both slots. We use identical speed tables for them. In future use, if
48 * DIMMs have fewer center values that require two separated tables, copy the
49 * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
50 */
51const struct board_specific_parameters *dimms[] = {
52 dimm0,
53 dimm0,
Haiying Wangc21617f2008-10-03 12:37:57 -040054};
55
Haiying Wangdfb49102008-10-03 12:36:55 -040056void fsl_ddr_board_options(memctl_options_t *popts,
Haiying Wangc21617f2008-10-03 12:37:57 -040057 dimm_params_t *pdimm,
58 unsigned int ctrl_num)
Kumar Gala6a8e5692008-08-26 15:01:35 -050059{
York Sun712cf7a2011-10-03 09:19:53 -070060 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
61 unsigned int i;
Haiying Wangc21617f2008-10-03 12:37:57 -040062 ulong ddr_freq;
Kumar Gala6a8e5692008-08-26 15:01:35 -050063
York Sun712cf7a2011-10-03 09:19:53 -070064 if (ctrl_num > 1) {
65 printf("Wrong parameter for controller number %d", ctrl_num);
66 return;
Haiying Wangc21617f2008-10-03 12:37:57 -040067 }
York Sun712cf7a2011-10-03 09:19:53 -070068 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
69 if (pdimm[i].n_ranks)
70 break;
71 }
72 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
73 return;
74
75 pbsp = dimms[ctrl_num];
Kumar Gala6a8e5692008-08-26 15:01:35 -050076
Haiying Wangc21617f2008-10-03 12:37:57 -040077 /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
78 * freqency and n_banks specified in board_specific_parameters table.
Kumar Gala6a8e5692008-08-26 15:01:35 -050079 */
Kumar Gala5df4b0a2011-01-31 20:36:02 -060080 ddr_freq = get_ddr_freq(0) / 1000000;
York Sun712cf7a2011-10-03 09:19:53 -070081 while (pbsp->datarate_mhz_high) {
82 if (pbsp->n_ranks == pdimm[i].n_ranks) {
83 if (ddr_freq <= pbsp->datarate_mhz_high) {
84 popts->clk_adjust = pbsp->clk_adjust;
85 popts->cpo_override = pbsp->cpo;
86 popts->write_data_delay =
87 pbsp->write_data_delay;
88 goto found;
Haiying Wangc21617f2008-10-03 12:37:57 -040089 }
York Sun712cf7a2011-10-03 09:19:53 -070090 pbsp_highest = pbsp;
Haiying Wangc21617f2008-10-03 12:37:57 -040091 }
York Sun712cf7a2011-10-03 09:19:53 -070092 pbsp++;
Haiying Wangc21617f2008-10-03 12:37:57 -040093 }
Kumar Gala6a8e5692008-08-26 15:01:35 -050094
York Sun712cf7a2011-10-03 09:19:53 -070095 if (pbsp_highest) {
96 printf("Error: board specific timing not found "
97 "for data rate %lu MT/s!\n"
98 "Trying to use the highest speed (%u) parameters\n",
99 ddr_freq, pbsp_highest->datarate_mhz_high);
100 popts->clk_adjust = pbsp_highest->clk_adjust;
101 popts->cpo_override = pbsp_highest->cpo;
102 popts->write_data_delay = pbsp_highest->write_data_delay;
103 } else {
104 panic("DIMM is not supported by this board");
York Sun939e5bf2011-06-27 13:30:55 -0700105 }
106
York Sun712cf7a2011-10-03 09:19:53 -0700107found:
Dave Liub4983e12008-11-21 16:31:43 +0800108 /* 2T timing enable */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530109 popts->twot_en = 1;
Kumar Gala6a8e5692008-08-26 15:01:35 -0500110}