blob: 2f16c89044ee98f9f1510a168c846214af673303 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiew72f56ad2008-01-15 13:54:09 -06002/*
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
TsiChungLiew72f56ad2008-01-15 13:54:09 -06004 */
5
6#ifndef _MCD_API_H
7#define _MCD_API_H
8
9/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
10#undef MCD_INCLUDE_EU
11
12/* Number of DMA channels */
13#define NCHANNELS 16
14
15/* Total number of variants */
16#ifdef MCD_INCLUDE_EU
17#define NUMOFVARIANTS 6
18#else
19#define NUMOFVARIANTS 4
20#endif
21
22/* Define sizes of the various tables */
23#define TASK_TABLE_SIZE (NCHANNELS*32)
24#define VAR_TAB_SIZE (128)
25#define CONTEXT_SAVE_SIZE (128)
26#define FUNCDESC_TAB_SIZE (256)
27
28#ifdef MCD_INCLUDE_EU
29#define FUNCDESC_TAB_NUM 16
30#else
31#define FUNCDESC_TAB_NUM 1
32#endif
33
34#ifndef DEFINESONLY
35
36/* Portability typedefs */
37#if 1
38#include "common.h"
39#else
40#ifndef s32
41typedef int s32;
42#endif
43#ifndef u32
44typedef unsigned int u32;
45#endif
46#ifndef s16
47typedef short s16;
48#endif
49#ifndef u16
50typedef unsigned short u16;
51#endif
52#ifndef s8
53typedef char s8;
54#endif
55#ifndef u8
56typedef unsigned char u8;
57#endif
58#endif
59
60/*
61 * These structures represent the internal registers of the
62 * multi-channel DMA
63 */
64struct dmaRegs_s {
65 u32 taskbar; /* task table base address */
66 u32 currPtr;
67 u32 endPtr;
68 u32 varTablePtr;
69 u16 dma_rsvd0;
70 u16 ptdControl; /* ptd control */
71 u32 intPending; /* interrupt pending */
72 u32 intMask; /* interrupt mask */
73 u16 taskControl[16]; /* task control */
74 u8 priority[32]; /* priority */
75 u32 initiatorMux; /* initiator mux control */
76 u32 taskSize0; /* task size control 0. */
77 u32 taskSize1; /* task size control 1. */
78 u32 dma_rsvd1; /* reserved */
79 u32 dma_rsvd2; /* reserved */
80 u32 debugComp1; /* debug comparator 1 */
81 u32 debugComp2; /* debug comparator 2 */
82 u32 debugControl; /* debug control */
83 u32 debugStatus; /* debug status */
84 u32 ptdDebug; /* priority task decode debug */
85 u32 dma_rsvd3[31]; /* reserved */
86};
87typedef volatile struct dmaRegs_s dmaRegs;
88
89#endif
90
91/* PTD contrl reg bits */
92#define PTD_CTL_TSK_PRI 0x8000
93#define PTD_CTL_COMM_PREFETCH 0x0001
94
95/* Task Control reg bits and field masks */
96#define TASK_CTL_EN 0x8000
97#define TASK_CTL_VALID 0x4000
98#define TASK_CTL_ALWAYS 0x2000
99#define TASK_CTL_INIT_MASK 0x1f00
100#define TASK_CTL_ASTRT 0x0080
101#define TASK_CTL_HIPRITSKEN 0x0040
102#define TASK_CTL_HLDINITNUM 0x0020
103#define TASK_CTL_ASTSKNUM_MASK 0x000f
104
105/* Priority reg bits and field masks */
106#define PRIORITY_HLD 0x80
107#define PRIORITY_PRI_MASK 0x07
108
109/* Debug Control reg bits and field masks */
110#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
111#define DBG_CTL_AUTO_ARM 0x00008000
112#define DBG_CTL_BREAK 0x00004000
113#define DBG_CTL_COMP1_TYP_MASK 0x00003800
114#define DBG_CTL_COMP2_TYP_MASK 0x00000070
115#define DBG_CTL_EXT_BREAK 0x00000004
116#define DBG_CTL_INT_BREAK 0x00000002
117
118/*
119 * PTD Debug reg selector addresses
120 * This reg must be written with a value to show the contents of
121 * one of the desired internal register.
122 */
123#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
124#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
125 have initiators asserted */
126
127/* General return values */
128#define MCD_OK 0
129#define MCD_ERROR -1
130#define MCD_TABLE_UNALIGNED -2
131#define MCD_CHANNEL_INVALID -3
132
133/* MCD_initDma input flags */
134#define MCD_RELOC_TASKS 0x00000001
135#define MCD_NO_RELOC_TASKS 0x00000000
136#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */
137
138/*
139 * MCD_dmaStatus Status Values for each channel:
140 * MCD_NO_DMA - No DMA has been requested since reset
141 * MCD_IDLE - DMA active, but the initiator is currently inactive
142 * MCD_RUNNING - DMA active, and the initiator is currently active
143 * MCD_PAUSED - DMA active but it is currently paused
144 * MCD_HALTED - the most recent DMA has been killed with MCD_killTask()
145 * MCD_DONE - the most recent DMA has completed
146 */
147#define MCD_NO_DMA 1
148#define MCD_IDLE 2
149#define MCD_RUNNING 3
150#define MCD_PAUSED 4
151#define MCD_HALTED 5
152#define MCD_DONE 6
153
154/* MCD_startDma parameter defines */
155
156/* Constants for the funcDesc parameter */
157/*
158 * MCD_NO_BYTE_SWAP - to disable byte swapping
159 * MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data
160 * MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data
161 * value being DMAed
162 * MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of
163 * each 32-bit data value DMAed
164 * MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed
165 * MCD_BIT_REV - reverse the bits of each byte DMAed
166 * MCD_CRC16 - to perform CRC-16 on DMAed data
167 * MCD_CRCCCITT - to perform CRC-CCITT on DMAed data
168 * MCD_CRC32 - to perform CRC-32 on DMAed data
169 * MCD_CSUMINET - to perform internet checksums on DMAed data
170 * MCD_NO_CSUM - to perform no checksumming
171 */
172#define MCD_NO_BYTE_SWAP 0x00045670
173#define MCD_BYTE_REVERSE 0x00076540
174#define MCD_U16_REVERSE 0x00067450
175#define MCD_U16_BYTE_REVERSE 0x00054760
176#define MCD_NO_BIT_REV 0x00000000
177#define MCD_BIT_REV 0x00088880
178/* CRCing: */
179#define MCD_CRC16 0xc0100000
180#define MCD_CRCCCITT 0xc0200000
181#define MCD_CRC32 0xc0300000
182#define MCD_CSUMINET 0xc0400000
183#define MCD_NO_CSUM 0xa0000000
184
185#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
186 MCD_NO_CSUM)
187#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
188
189/* Constants for the flags parameter */
190#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
191#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
192#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */
193#define MCD_TT_FLAGS_MASK 0x000000ff
194#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
195
196#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
197#define MCD_CHAIN_DMA /* TBD */
198#define MCD_EU_DMA /* TBD */
199#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
200#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
201
202/* these flags are valid for MCD_startDma and the chained buffer descriptors */
203/*
204 * MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl
205 * MCD_WRAP - to tell the FEC Dmas to wrap to the first BD
206 * MCD_INTERRUPT - to generate an interrupt after completion of the DMA
207 * MCD_END_FRAME - tell the DMA to end the frame when transferring
208 * last byte of data in buffer
209 * MCD_CRC_RESTART - to empty out the accumulated checksum prior to
210 * performing the DMA
211 */
212#define MCD_BUF_READY 0x80000000
213#define MCD_WRAP 0x20000000
214#define MCD_INTERRUPT 0x10000000
215#define MCD_END_FRAME 0x08000000
216#define MCD_CRC_RESTART 0x40000000
217
218/* Defines for the FEC buffer descriptor control/status word*/
219#define MCD_FEC_BUF_READY 0x8000
220#define MCD_FEC_WRAP 0x2000
221#define MCD_FEC_INTERRUPT 0x1000
222#define MCD_FEC_END_FRAME 0x0800
223
224/* Defines for general intuitiveness */
225
226#define MCD_TRUE 1
227#define MCD_FALSE 0
228
229/* Three different cases for destination and source. */
230#define MINUS1 -1
231#define ZERO 0
232#define PLUS1 1
233
234#ifndef DEFINESONLY
235
236/* Task Table Entry struct*/
237typedef struct {
238 u32 TDTstart; /* task descriptor table start */
239 u32 TDTend; /* task descriptor table end */
240 u32 varTab; /* variable table start */
241 u32 FDTandFlags; /* function descriptor table start & flags */
242 volatile u32 descAddrAndStatus;
243 volatile u32 modifiedVarTab;
244 u32 contextSaveSpace; /* context save space start */
245 u32 literalBases;
246} TaskTableEntry;
247
248/* Chained buffer descriptor:
249 * flags - flags describing the DMA
250 * csumResult - checksum performed since last checksum reset
251 * srcAddr - the address to move data from
252 * destAddr - the address to move data to
253 * lastDestAddr - the last address written to
254 * dmaSize - the no of bytes to xfer independent of the xfer sz
255 * next - next buffer descriptor in chain
256 * info - private info about this descriptor; DMA does not affect it
257 */
258typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
259struct MCD_bufDesc_struct {
260 u32 flags;
261 u32 csumResult;
262 s8 *srcAddr;
263 s8 *destAddr;
264 s8 *lastDestAddr;
265 u32 dmaSize;
266 MCD_bufDesc *next;
267 u32 info;
268};
269
270/* Progress Query struct:
271 * lastSrcAddr - the most-recent or last, post-increment source address
272 * lastDestAddr - the most-recent or last, post-increment destination address
273 * dmaSize - the amount of data transferred for the current buffer
274 * currBufDesc - pointer to the current buffer descriptor being DMAed
275 */
276
277typedef volatile struct MCD_XferProg_struct {
278 s8 *lastSrcAddr;
279 s8 *lastDestAddr;
280 u32 dmaSize;
281 MCD_bufDesc *currBufDesc;
282} MCD_XferProg;
283
284/* FEC buffer descriptor */
285typedef volatile struct MCD_bufDescFec_struct {
286 u16 statCtrl;
287 u16 length;
288 u32 dataPointer;
289} MCD_bufDescFec;
290
291/*************************************************************************/
292/* API function Prototypes - see MCD_dmaApi.c for further notes */
293
294/* MCD_startDma starts a particular kind of DMA:
295 * srcAddr - the channel on which to run the DMA
296 * srcIncr - the address to move data from, or buffer-descriptor address
297 * destAddr - the amount to increment the source address per transfer
298 * destIncr - the address to move data to
299 * dmaSize - the amount to increment the destination address per transfer
300 * xferSize - the number bytes in of each data movement (1, 2, or 4)
301 * initiator - what device initiates the DMA
302 * priority - priority of the DMA
303 * flags - flags describing the DMA
304 * funcDesc - description of byte swapping, bit swapping, and CRC actions
305 */
306int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
307 s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
308 int priority, u32 flags, u32 funcDesc);
309
310/*
311 * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
312 * registers, relocating and creating the appropriate task structures, and
313 * setting up some global settings
314 */
315int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
316
317/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
318int MCD_dmaStatus(int channel);
319
320/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
321int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
322
323/*
324 * MCD_killDma() halts the DMA on the requested channel, without any
325 * intention of resuming the DMA.
326 */
327int MCD_killDma(int channel);
328
329/*
330 * MCD_continDma() continues a DMA which as stopped due to encountering an
331 * unready buffer descriptor.
332 */
333int MCD_continDma(int channel);
334
335/*
336 * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
337 * running on that channel).
338 */
339int MCD_pauseDma(int channel);
340
341/*
342 * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
343 * running on that channel).
344 */
345int MCD_resumeDma(int channel);
346
347/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
348int MCD_csumQuery(int channel, u32 * csum);
349
350/*
351 * MCD_getCodeSize provides the packed size required by the microcoded task
352 * and structures.
353 */
354int MCD_getCodeSize(void);
355
356/*
357 * MCD_getVersion provides a pointer to a version string and returns a
358 * version number.
359 */
360int MCD_getVersion(char **longVersion);
361
362/* macro for setting a location in the variable table */
363#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
364/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
365 so I'm avoiding surrounding it with "do {} while(0)" */
366
367#endif /* DEFINESONLY */
368
369#endif /* _MCD_API_H */