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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
stroesecd42dee2004-12-16 17:56:09 +00002/*
3 * mcf5249.h -- Definitions for Motorola Coldfire 5249
4 *
5 * Based on mcf5272sim.h of uCLinux distribution:
6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
stroesecd42dee2004-12-16 17:56:09 +00008 */
9
stroesecd42dee2004-12-16 17:56:09 +000010#ifndef mcf5249_h
11#define mcf5249_h
12/****************************************************************************/
13
14/*
15 * useful definitions for reading/writing MBAR offset memory
16 */
Tom Rini65cc0e22022-11-16 13:10:41 -050017#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x))
18#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y
19#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y
20#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y
21#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x))
22#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) = y
23#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR2 + x)) = y
24#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR2 + x)) = y
stroesecd42dee2004-12-16 17:56:09 +000025
26/*
27 * Size of internal RAM
28 */
29
TsiChungLiew56115662007-08-15 19:38:15 -050030#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
31#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
stroesecd42dee2004-12-16 17:56:09 +000032
33/*
34 * Define the 5249 SIM register set addresses.
35 */
36
37/*****************
38 ***** MBAR1 *****
39 *****************/
TsiChungLiew56115662007-08-15 19:38:15 -050040#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
41#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */
42#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
43#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020044#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
stroesecd42dee2004-12-16 17:56:09 +000045
TsiChungLiew56115662007-08-15 19:38:15 -050046#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
47#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
48#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
49#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
50#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
51#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
52#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
53#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
54#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
55#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
56#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
57#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
58#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
stroesecd42dee2004-12-16 17:56:09 +000059
TsiChungLiew56115662007-08-15 19:38:15 -050060#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
61#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
stroesecd42dee2004-12-16 17:56:09 +000062
TsiChungLiew56115662007-08-15 19:38:15 -050063#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
64#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
65#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
66#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
67#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
stroesecd42dee2004-12-16 17:56:09 +000068
69/*****************
70 ***** MBAR2 *****
71 *****************/
72
73/* GPIO Addresses
74 * Note: These are offset from MBAR2!
75 */
TsiChungLiew56115662007-08-15 19:38:15 -050076#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
77#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */
78#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */
79#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
80#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
81#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
82#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
83#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
stroesecd42dee2004-12-16 17:56:09 +000084
TsiChungLiew56115662007-08-15 19:38:15 -050085#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
86#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
87#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
stroesecd42dee2004-12-16 17:56:09 +000088
TsiChungLiew56115662007-08-15 19:38:15 -050089#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
90#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
91#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
stroesecd42dee2004-12-16 17:56:09 +000092
TsiChungLiew56115662007-08-15 19:38:15 -050093#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
94#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
95#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
96#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
97#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
98#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
99#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
100#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
stroesecd42dee2004-12-16 17:56:09 +0000101
TsiChungLiew56115662007-08-15 19:38:15 -0500102#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
103#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
stroesecd42dee2004-12-16 17:56:09 +0000104
TsiChungLiew56115662007-08-15 19:38:15 -0500105#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
106#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
stroesecd42dee2004-12-16 17:56:09 +0000107
TsiChungLiew56115662007-08-15 19:38:15 -0500108#define MCFSIM_PLLCR 0x180 /* PLL Control register */
stroesecd42dee2004-12-16 17:56:09 +0000109
stroesecd42dee2004-12-16 17:56:09 +0000110/*
111 * Some symbol defines for the above...
112 */
113#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
114#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
115#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
116#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
117#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
118#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
119/* XXX - If needed, DMA ICRs go here */
120#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
121
122/*
123 * Bit definitions for the ICR family of registers.
124 */
TsiChungLiew56115662007-08-15 19:38:15 -0500125#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
126#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
127#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
128#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
129#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
130#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
131#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
132#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
133#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
stroesecd42dee2004-12-16 17:56:09 +0000134
TsiChungLiew56115662007-08-15 19:38:15 -0500135#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
136#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
137#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
138#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
stroesecd42dee2004-12-16 17:56:09 +0000139
140/*
141 * Macros to read/set IMR register. It is 32 bits on the 5249.
142 */
143
144#define mcf_getimr() \
145 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
146
147#define mcf_setimr(imr) \
148 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
149
TsiChungLiew56115662007-08-15 19:38:15 -0500150#endif /* mcf5249_h */