| Nishanth Menon | 9a0f400 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 1 | /* |
| 2 | * ti_armv7_omap.h |
| 3 | * |
| 4 | * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | * |
| 8 | * The various ARMv7 SoCs from TI all share a number of IP blocks when |
| 9 | * implementing a given feature. This is meant to isolate the features |
| 10 | * that are based on OMAP architecture. |
| 11 | */ |
| 12 | #ifndef __CONFIG_TI_ARMV7_OMAP_H__ |
| 13 | #define __CONFIG_TI_ARMV7_OMAP_H__ |
| 14 | |
| Nishanth Menon | 9a0f400 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 15 | /* I2C IP block */ |
| 16 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 |
| 17 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 |
| 18 | #define CONFIG_SYS_I2C_OMAP24XX |
| 19 | |
| Nishanth Menon | 9a0f400 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 20 | /* SPI IP Block */ |
| 21 | #define CONFIG_OMAP3_SPI |
| 22 | |
| Nishanth Menon | 9a0f400 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 23 | /* |
| 24 | * GPMC NAND block. We support 1 device and the physical address to |
| 25 | * access CS0 at is 0x8000000. |
| 26 | */ |
| 27 | #ifdef CONFIG_NAND |
| 28 | #define CONFIG_NAND_OMAP_GPMC |
| 29 | #ifndef CONFIG_SYS_NAND_BASE |
| 30 | #define CONFIG_SYS_NAND_BASE 0x8000000 |
| 31 | #endif |
| 32 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 33 | #define CONFIG_CMD_NAND |
| 34 | #endif |
| 35 | |
| 36 | /* Now for the remaining common defines */ |
| 37 | #include <configs/ti_armv7_common.h> |
| 38 | |
| 39 | #endif /* __CONFIG_TI_ARMV7_OMAP_H__ */ |