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wdenk384cc682005-04-03 22:35:21 +00001 /*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
28#include <common.h>
29#include <pci.h>
30#include <asm/processor.h>
31#include <asm/immap_85xx.h>
32#include <spd.h>
33
34#if defined(CONFIG_DDR_ECC)
35extern void ddr_enable_ecc(unsigned int dram_size);
36#endif
37
38extern long int spd_sdram(void);
39
40void local_bus_init(void);
41void sdram_init(void);
42long int fixed_sdram(void);
43
44
45int board_early_init_f (void)
46{
47#if defined(CONFIG_PCI)
Kumar Gala04db4002007-11-29 02:10:09 -060048 volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
wdenk384cc682005-04-03 22:35:21 +000049
50 pci->peer &= 0xffffffdf; /* disable master abort */
51#endif
52
53 return 0;
54}
55
56int checkboard (void)
57{
58 puts("Board: MicroSys PM854\n");
59
60#ifdef CONFIG_PCI
61 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
62 CONFIG_SYS_CLK_FREQ / 1000000);
63#else
64 printf(" PCI1: disabled\n");
65#endif
66
67 /*
68 * Initialize local bus.
69 */
70 local_bus_init();
71
72 return 0;
73}
74
75
76long int
77initdram(int board_type)
78{
79 long dram_size = 0;
80 extern long spd_sdram (void);
wdenk384cc682005-04-03 22:35:21 +000081
82 puts("Initializing\n");
83
84#if defined(CONFIG_DDR_DLL)
85 {
Kumar Galaf59b55a2007-11-27 23:25:02 -060086 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
wdenk384cc682005-04-03 22:35:21 +000087 int i,x;
wdenk8b0bfc62005-04-03 23:11:38 +000088
wdenk384cc682005-04-03 22:35:21 +000089 x = 10;
wdenk8b0bfc62005-04-03 23:11:38 +000090
wdenk384cc682005-04-03 22:35:21 +000091 /*
92 * Work around to stabilize DDR DLL
93 */
94 gur->ddrdllcr = 0x81000000;
95 asm("sync;isync;msync");
96 udelay (200);
97 while (gur->ddrdllcr != 0x81000100)
98 {
99 gur->devdisr = gur->devdisr | 0x00010000;
100 asm("sync;isync;msync");
101 for (i=0; i<x; i++)
102 ;
103 gur->devdisr = gur->devdisr & 0xfff7ffff;
104 asm("sync;isync;msync");
105 x++;
106 }
wdenk8b0bfc62005-04-03 23:11:38 +0000107 }
wdenk384cc682005-04-03 22:35:21 +0000108#endif
109
110#if defined(CONFIG_SPD_EEPROM)
111 dram_size = spd_sdram ();
112#else
113 dram_size = fixed_sdram ();
114#endif
115
116#if defined(CONFIG_DDR_ECC)
117 /*
118 * Initialize and enable DDR ECC.
119 */
120 ddr_enable_ecc(dram_size);
121#endif
122 puts(" DDR: ");
123 return dram_size;
124}
125
126
127/*
128 * Initialize Local Bus
129 */
130
131void
132local_bus_init(void)
133{
Kumar Galaf59b55a2007-11-27 23:25:02 -0600134 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
Kumar Gala04db4002007-11-29 02:10:09 -0600135 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
wdenk384cc682005-04-03 22:35:21 +0000136
137 uint clkdiv;
138 uint lbc_hz;
139 sys_info_t sysinfo;
140
141 /*
142 * Errata LBC11.
143 * Fix Local Bus clock glitch when DLL is enabled.
144 *
145 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
146 * If localbus freq is > 133Mhz, DLL can be safely enabled.
147 * Between 66 and 133, the DLL is enabled with an override workaround.
148 */
149
150 get_sys_info(&sysinfo);
151 clkdiv = lbc->lcrr & 0x0f;
152 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
153
154 if (lbc_hz < 66) {
155 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
156
157 } else if (lbc_hz >= 133) {
158 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
159
160 } else {
161 /*
162 * On REV1 boards, need to change CLKDIV before enable DLL.
163 * Default CLKDIV is 8, change it to 4 temporarily.
164 */
165 uint pvr = get_pvr();
166 uint temp_lbcdll = 0;
167
168 if (pvr == PVR_85xx_REV1) {
169 /* FIXME: Justify the high bit here. */
170 lbc->lcrr = 0x10000004;
171 }
172
173 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
174 udelay(200);
175
176 /*
177 * Sample LBC DLL ctrl reg, upshift it to set the
178 * override bits.
179 */
180 temp_lbcdll = gur->lbcdllcr;
181 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
182 asm("sync;isync;msync");
183 }
184}
185
186
187#if defined(CFG_DRAM_TEST)
188int testdram (void)
189{
190 uint *pstart = (uint *) CFG_MEMTEST_START;
191 uint *pend = (uint *) CFG_MEMTEST_END;
192 uint *p;
193
194 printf("SDRAM test phase 1:\n");
195 for (p = pstart; p < pend; p++)
196 *p = 0xaaaaaaaa;
197
198 for (p = pstart; p < pend; p++) {
199 if (*p != 0xaaaaaaaa) {
200 printf ("SDRAM test fails at: %08x\n", (uint) p);
201 return 1;
202 }
203 }
204
205 printf("SDRAM test phase 2:\n");
206 for (p = pstart; p < pend; p++)
207 *p = 0x55555555;
208
209 for (p = pstart; p < pend; p++) {
210 if (*p != 0x55555555) {
211 printf ("SDRAM test fails at: %08x\n", (uint) p);
212 return 1;
213 }
214 }
215
216 printf("SDRAM test passed.\n");
217 return 0;
218}
219#endif
220
221
222#if !defined(CONFIG_SPD_EEPROM)
223/*************************************************************************
224 * fixed sdram init -- doesn't use serial presence detect.
225 ************************************************************************/
226long int fixed_sdram (void)
227{
228 #ifndef CFG_RAMBOOT
Kumar Gala04db4002007-11-29 02:10:09 -0600229 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
wdenk384cc682005-04-03 22:35:21 +0000230
231 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
232 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
233 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
234 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
235 ddr->sdram_mode = CFG_DDR_MODE;
236 ddr->sdram_interval = CFG_DDR_INTERVAL;
237 #if defined (CONFIG_DDR_ECC)
238 ddr->err_disable = 0x0000000D;
239 ddr->err_sbe = 0x00ff0000;
240 #endif
241 asm("sync;isync;msync");
242 udelay(500);
243 #if defined (CONFIG_DDR_ECC)
244 /* Enable ECC checking */
245 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
246 #else
247 ddr->sdram_cfg = CFG_DDR_CONTROL;
248 #endif
249 asm("sync; isync; msync");
250 udelay(500);
251 #endif
252 return CFG_SDRAM_SIZE * 1024 * 1024;
253}
254#endif /* !defined(CONFIG_SPD_EEPROM) */
255
256
257#if defined(CONFIG_PCI)
258/*
259 * Initialize PCI Devices, report devices found.
260 */
261
262#ifndef CONFIG_PCI_PNP
263static struct pci_config_table pci_pm854_config_table[] = {
264 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
265 PCI_IDSEL_NUMBER, PCI_ANY_ID,
266 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
267 PCI_ENET0_MEMADDR,
268 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
269 } },
270 { }
271};
272#endif
273
274
275static struct pci_controller hose = {
276#ifndef CONFIG_PCI_PNP
277 config_table: pci_pm854_config_table,
278#endif
279};
280
281#endif /* CONFIG_PCI */
282
283
284void
285pci_init_board(void)
286{
287#ifdef CONFIG_PCI
wdenk384cc682005-04-03 22:35:21 +0000288 pci_mpc85xx_init(&hose);
289#endif /* CONFIG_PCI */
290}