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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuration settings for the WindRiver SBC8260 board.
14 * See http://www.windriver.com/products/html/sbc8260.html
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
wdenkfe8c2802002-11-03 00:38:21 +000038#undef DEBUG /* General debug */
39#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
40
wdenk78137c32003-09-15 18:00:00 +000041#undef CONFIG_LOGBUFFER /* External logbuffer support */
42
wdenkfe8c2802002-11-03 00:38:21 +000043/*****************************************************************************
44 *
45 * These settings must match the way _your_ board is set up
46 *
47 *****************************************************************************/
48
49/* What is the oscillator's (UX2) frequency in Hz? */
50#define CONFIG_8260_CLKIN 66666600
51
52/*-----------------------------------------------------------------------
53 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
54 *-----------------------------------------------------------------------
55 * What should MODCK_H be? It is dependent on the oscillator
56 * frequency, MODCK[1-3], and desired CPM and core frequencies.
57 * Here are some example values (all frequencies are in MHz):
58 *
59 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
60 * ------- ---------- --- --- ---- ----- ----- -----
61 * 0x1 0x5 33 100 133 Open Close Open
62 * 0x1 0x6 33 100 166 Open Open Close
63 * 0x1 0x7 33 100 200 Open Open Open
64 *
65 * 0x2 0x2 33 133 133 Close Open Close
66 * 0x2 0x3 33 133 166 Close Open Open
67 * 0x2 0x4 33 133 200 Open Close Close
68 * 0x2 0x5 33 133 233 Open Close Open
69 * 0x2 0x6 33 133 266 Open Open Close
70 *
71 * 0x5 0x5 66 133 133 Open Close Open
72 * 0x5 0x6 66 133 166 Open Open Close
73 * 0x5 0x7 66 133 200 Open Open Open
74 * 0x6 0x0 66 133 233 Close Close Close
75 * 0x6 0x1 66 133 266 Close Close Open
76 * 0x6 0x2 66 133 300 Close Open Close
77 */
78#define CFG_SBC_MODCK_H 0x05
79
80/* Define this if you want to boot from 0x00000100. If you don't define
81 * this, you will need to program the bootloader to 0xfff00000, and
82 * get the hardware reset config words at 0xfe000000. The simplest
83 * way to do that is to program the bootloader at both addresses.
84 * It is suggested that you just let U-Boot live at 0x00000000.
85 */
86#define CFG_SBC_BOOT_LOW 1
87
88/* What should the base address of the main FLASH be and how big is
89 * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk
90 * The main FLASH is whichever is connected to *CS0.
91 */
92#define CFG_FLASH0_BASE 0x40000000
93#define CFG_FLASH0_SIZE 2
94
95/* What should the base address of the secondary FLASH be and how big
96 * is it (in Mbytes)? The secondary FLASH is whichever is connected
97 * to *CS6.
98 */
99#define CFG_FLASH1_BASE 0x60000000
100#define CFG_FLASH1_SIZE 2
101
102/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
103 */
104#define CONFIG_VERY_BIG_RAM 1
105
106/* What should be the base address of SDRAM DIMM and how big is
107 * it (in Mbytes)? This will normally auto-configure via the SPD.
108*/
109#define CFG_SDRAM0_BASE 0x00000000
110#define CFG_SDRAM0_SIZE 64
111
112/*
113 * Memory map example with 64 MB DIMM:
114 *
115 * 0x0000 0000 Exception Vector code, 8k
116 * :
117 * 0x0000 1FFF
118 * 0x0000 2000 Free for Application Use
119 * :
120 * :
121 *
122 * :
123 * :
124 * 0x03F5 FF30 Monitor Stack (Growing downward)
125 * Monitor Stack Buffer (0x80)
126 * 0x03F5 FFB0 Board Info Data
127 * 0x03F6 0000 Malloc Arena
128 * : CFG_ENV_SECT_SIZE, 16k
129 * : CFG_MALLOC_LEN, 128k
130 * 0x03FC 0000 RAM Copy of Monitor Code
131 * : CFG_MONITOR_LEN, 256k
132 * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
133 */
134
135#define CONFIG_POST (CFG_POST_MEMORY | \
136 CFG_POST_CPU)
137
138
139/*
140 * select serial console configuration
141 *
142 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
143 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
144 * for SCC).
145 *
146 * if CONFIG_CONS_NONE is defined, then the serial console routines must
147 * defined elsewhere.
148 */
149#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
150#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
151#undef CONFIG_CONS_NONE /* define if console on neither */
152#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
153
154/*
155 * select ethernet configuration
156 *
157 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
158 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
159 * for FCC)
160 *
161 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500162 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkfe8c2802002-11-03 00:38:21 +0000163 */
164
165#undef CONFIG_ETHER_ON_SCC
166#define CONFIG_ETHER_ON_FCC
167#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
168
169#ifdef CONFIG_ETHER_ON_SCC
170#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
171#endif /* CONFIG_ETHER_ON_SCC */
172
173#ifdef CONFIG_ETHER_ON_FCC
174#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
wdenk78137c32003-09-15 18:00:00 +0000175#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
wdenkfe8c2802002-11-03 00:38:21 +0000176#define CONFIG_MII /* MII PHY management */
177#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
178/*
179 * Port pins used for bit-banged MII communictions (if applicable).
180 */
181
182#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
183#define MDIO_ACTIVE (iop->pdir |= 0x40000000)
184#define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
185#define MDIO_READ ((iop->pdat & 0x40000000) != 0)
186
187#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
188 else iop->pdat &= ~0x40000000
189
190#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
191 else iop->pdat &= ~0x80000000
192
193#define MIIDELAY udelay(50)
194#endif /* CONFIG_ETHER_ON_FCC */
195
196#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
197
198/*
199 * - RX clk is CLK11
200 * - TX clk is CLK12
201 */
202# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
203
204#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
205
206/*
207 * - Rx-CLK is CLK13
208 * - Tx-CLK is CLK14
209 * - Select bus for bd/buffers (see 28-13)
210 * - Enable Full Duplex in FSMR
211 */
212# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
213# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
214# define CFG_CPMFCR_RAMTYPE 0
215# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
216
217#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
218
219#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
220
221/*
222 * Configure for RAM tests.
223 */
224#undef CFG_DRAM_TEST /* calls other tests in board.c */
225
226
227/*
228 * Status LED for power up status feedback.
229 */
230#define CONFIG_STATUS_LED 1 /* Status LED enabled */
231
232#define STATUS_LED_PAR im_ioport.iop_ppara
233#define STATUS_LED_DIR im_ioport.iop_pdira
234#define STATUS_LED_ODR im_ioport.iop_podra
235#define STATUS_LED_DAT im_ioport.iop_pdata
236
237#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
238#define STATUS_LED_PERIOD (CFG_HZ)
239#define STATUS_LED_STATE STATUS_LED_OFF
240#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
241#define STATUS_LED_PERIOD1 (CFG_HZ)
242#define STATUS_LED_STATE1 STATUS_LED_OFF
243#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
244#define STATUS_LED_PERIOD2 (CFG_HZ/2)
245#define STATUS_LED_STATE2 STATUS_LED_ON
246
247#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
248
249#define STATUS_LED_YELLOW 0
250#define STATUS_LED_GREEN 1
251#define STATUS_LED_RED 2
252#define STATUS_LED_BOOT 1
253
254
255/*
wdenk1d0350e2002-11-11 21:14:20 +0000256 * Select SPI support configuration
wdenkfe8c2802002-11-03 00:38:21 +0000257 */
wdenk1d0350e2002-11-11 21:14:20 +0000258#define CONFIG_SOFT_SPI /* Enable SPI driver */
259#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */
wdenk8bde7f72003-06-27 21:31:46 +0000260#undef DEBUG_SPI /* Disable SPI debugging */
261
wdenkfe8c2802002-11-03 00:38:21 +0000262/*
263 * Software (bit-bang) SPI driver configuration
264 */
265#ifdef CONFIG_SOFT_SPI
266
267/*
268 * Software (bit-bang) SPI driver configuration
269 */
270#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
271#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
272#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
273
274#undef SPI_INIT /* no port initialization needed */
275#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
276#define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
wdenk8bde7f72003-06-27 21:31:46 +0000277 else immr->im_ioport.iop_pdatd &= ~I2C_MOSI
wdenkfe8c2802002-11-03 00:38:21 +0000278#define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
wdenk8bde7f72003-06-27 21:31:46 +0000279 else immr->im_ioport.iop_pdatd &= ~I2C_SCLK
wdenk1d0350e2002-11-11 21:14:20 +0000280#define SPI_DELAY /* No delay is needed */
wdenkfe8c2802002-11-03 00:38:21 +0000281#endif /* CONFIG_SOFT_SPI */
282
283
284/*
285 * select I2C support configuration
286 *
287 * Supported configurations are {none, software, hardware} drivers.
288 * If the software driver is chosen, there are some additional
289 * configuration items that the driver uses to drive the port pins.
290 */
291#undef CONFIG_HARD_I2C /* I2C with hardware support */
292#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
293#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
294#define CFG_I2C_SLAVE 0x7F
295
296/*
297 * Software (bit-bang) I2C driver configuration
298 */
299#ifdef CONFIG_SOFT_I2C
300#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
301#define I2C_ACTIVE (iop->pdir |= 0x00010000)
302#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
303#define I2C_READ ((iop->pdat & 0x00010000) != 0)
304#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
305 else iop->pdat &= ~0x00010000
306#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
307 else iop->pdat &= ~0x00020000
308#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
309#endif /* CONFIG_SOFT_I2C */
310
311/* Define this to reserve an entire FLASH sector for
312 * environment variables. Otherwise, the environment will be
313 * put in the same sector as U-Boot, and changing variables
314 * will erase U-Boot temporarily
315 */
316#define CFG_ENV_IN_OWN_SECT 1
317
318/* Define this to contain any number of null terminated strings that
319 * will be part of the default enviroment compiled into the boot image.
320 */
321#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk78137c32003-09-15 18:00:00 +0000322"quiet=0\0" \
323"serverip=192.168.123.205\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000324"ipaddr=192.168.123.203\0" \
325"checkhostname=VR8500\0" \
326"reprog="\
wdenk78137c32003-09-15 18:00:00 +0000327 "bootp; " \
wdenkfe8c2802002-11-03 00:38:21 +0000328 "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
329 "protect off 60000000 6003FFFF; " \
330 "erase 60000000 6003FFFF; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100331 "cp.b 140000 60000000 ${filesize}; " \
wdenkfe8c2802002-11-03 00:38:21 +0000332 "protect on 60000000 6003FFFF\0" \
333"copyenv="\
334 "protect off 60040000 6004FFFF; " \
335 "erase 60040000 6004FFFF; " \
336 "cp.b 40040000 60040000 10000; " \
337 "protect on 60040000 6004FFFF\0" \
338"copyprog="\
339 "protect off 60000000 6003FFFF; " \
340 "erase 60000000 6003FFFF; " \
341 "cp.b 40000000 60000000 40000; " \
342 "protect on 60000000 6003FFFF\0" \
343"zapenv="\
344 "protect off 40040000 4004FFFF; " \
345 "erase 40040000 4004FFFF; " \
346 "protect on 40040000 4004FFFF\0" \
347"zapotherenv="\
348 "protect off 60040000 6004FFFF; " \
349 "erase 60040000 6004FFFF; " \
350 "protect on 60040000 6004FFFF\0" \
351"root-on-initrd="\
352 "setenv bootcmd "\
353 "version\\;" \
354 "echo\\;" \
355 "bootp\\;" \
356 "setenv bootargs root=/dev/ram0 rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100357 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000358 "run boot-hook\\;" \
359 "bootm\0" \
360"root-on-initrd-debug="\
361 "setenv bootcmd "\
362 "version\\;" \
363 "echo\\;" \
364 "bootp\\;" \
365 "setenv bootargs root=/dev/ram0 rw debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100366 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000367 "run debug-hook\\;" \
368 "run boot-hook\\;" \
369 "bootm\0" \
370"root-on-nfs="\
371 "setenv bootcmd "\
372 "version\\;" \
373 "echo\\;" \
374 "bootp\\;" \
375 "setenv bootargs root=/dev/nfs rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100376 "nfsroot=\\${serverip}:\\${rootpath} " \
377 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000378 "run boot-hook\\;" \
379 "bootm\0" \
380"root-on-nfs-debug="\
381 "setenv bootcmd "\
382 "version\\;" \
383 "echo\\;" \
384 "bootp\\;" \
385 "setenv bootargs root=/dev/nfs rw debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100386 "nfsroot=\\${serverip}:\\${rootpath} " \
387 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000388 "run debug-hook\\;" \
389 "run boot-hook\\;" \
390 "bootm\0" \
391"debug-checkout="\
392 "setenv checkhostname;" \
393 "setenv ethaddr 00:09:70:00:00:01;" \
394 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100395 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
396 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000397 "run debug-hook;" \
398 "run boot-hook;" \
399 "bootm\0" \
400"debug-hook="\
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100401 "echo ipaddr ${ipaddr};" \
402 "echo serverip ${serverip};" \
403 "echo gatewayip ${gatewayip};" \
404 "echo netmask ${netmask};" \
405 "echo hostname ${hostname}\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000406"ana=run adc ; run dac\0" \
407"adc=run adc-12 ; run adc-34\0" \
408"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
409"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
410"dac=echo ### DAC ; imd.b 11 81 5\0" \
wdenk78137c32003-09-15 18:00:00 +0000411"boot-hook=echo\0"
wdenkfe8c2802002-11-03 00:38:21 +0000412
413/* What should the console's baud rate be? */
414#define CONFIG_BAUDRATE 9600
415
416/* Ethernet MAC address */
417#define CONFIG_ETHADDR 00:09:70:00:00:00
418
419/* The default Ethernet MAC address can be overwritten just once */
420#ifdef CONFIG_ETHADDR
421#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
422#endif
423
424/*
425 * Define this to do some miscellaneous board-specific initialization.
426 */
427#define CONFIG_MISC_INIT_R
428
429/* Set to a positive value to delay for running BOOTCOMMAND */
430#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
431
432/* Be selective on what keys can delay or stop the autoboot process
433 * To stop use: " "
434 */
435#define CONFIG_AUTOBOOT_KEYED
436#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
437#define CONFIG_AUTOBOOT_STOP_STR " "
438#undef CONFIG_AUTOBOOT_DELAY_STR
439#define CONFIG_ZERO_BOOTDELAY_CHECK
440#define DEBUG_BOOTKEYS 0
441
442/* Define a command string that is automatically executed when no character
443 * is read on the console interface withing "Boot Delay" after reset.
444 */
wdenkb79a11c2004-03-25 15:14:43 +0000445#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
446#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenkfe8c2802002-11-03 00:38:21 +0000447
wdenk42dfe7a2004-03-14 22:25:36 +0000448#ifdef CONFIG_BOOT_ROOT_INITRD
wdenkfe8c2802002-11-03 00:38:21 +0000449#define CONFIG_BOOTCOMMAND \
450 "version;" \
451 "echo;" \
452 "bootp;" \
453 "setenv bootargs root=/dev/ram0 rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100454 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000455 "run boot-hook;" \
456 "bootm"
457#endif /* CONFIG_BOOT_ROOT_INITRD */
458
wdenk42dfe7a2004-03-14 22:25:36 +0000459#ifdef CONFIG_BOOT_ROOT_NFS
wdenkfe8c2802002-11-03 00:38:21 +0000460#define CONFIG_BOOTCOMMAND \
461 "version;" \
462 "echo;" \
463 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100464 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
465 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000466 "run boot-hook;" \
467 "bootm"
468#endif /* CONFIG_BOOT_ROOT_NFS */
469
470#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
471
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500472/*
473 * BOOTP options
wdenkfe8c2802002-11-03 00:38:21 +0000474 */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500475#define CONFIG_BOOTP_SUBNETMASK
476#define CONFIG_BOOTP_GATEWAY
477#define CONFIG_BOOTP_HOSTNAME
478#define CONFIG_BOOTP_BOOTPATH
479#define CONFIG_BOOTP_BOOTFILESIZE
480#define CONFIG_BOOTP_DNS
481#define CONFIG_BOOTP_DNS2
482#define CONFIG_BOOTP_SEND_HOSTNAME
483
wdenkfe8c2802002-11-03 00:38:21 +0000484
485/* undef this to save memory */
486#define CFG_LONGHELP
487
488/* Monitor Command Prompt */
489#define CFG_PROMPT "=> "
490
491#undef CFG_HUSH_PARSER
492#ifdef CFG_HUSH_PARSER
493#define CFG_PROMPT_HUSH_PS2 "> "
494#endif
495
wdenk1d0350e2002-11-11 21:14:20 +0000496/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
497 * of an image is printed by image commands like bootm or iminfo.
498 */
499#define CONFIG_TIMESTAMP
500
wdenk42d1f032003-10-15 23:53:47 +0000501/* If this variable is defined, an environment variable named "ver"
wdenk78137c32003-09-15 18:00:00 +0000502 * is created by U-Boot showing the U-Boot version.
503 */
504#define CONFIG_VERSION_VARIABLE
505
Jon Loeliger46da1e92007-07-04 22:33:30 -0500506
507/*
508 * Command line configuration.
509 */
510#include <config_cmd_default.h>
511
512#define CONFIG_CMD_ELF
513#define CONFIG_CMD_ASKENV
514#define CONFIG_CMD_I2C
515#define CONFIG_CMD_SPI
516#define CONFIG_CMD_SDRAM
517#define CONFIG_CMD_REGINFO
518#define CONFIG_CMD_IMMAP
519#define CONFIG_CMD_IRQ
520#define CONFIG_CMD_PING
521
522#undef CONFIG_CMD_KGDB
523
wdenkfe8c2802002-11-03 00:38:21 +0000524#ifdef CONFIG_ETHER_ON_FCC
Jon Loeliger46da1e92007-07-04 22:33:30 -0500525#define CONFIG_CMD_MII
526#endif
527
wdenkfe8c2802002-11-03 00:38:21 +0000528
529/* Where do the internal registers live? */
530#define CFG_IMMR 0xF0000000
531
wdenk78137c32003-09-15 18:00:00 +0000532#undef CONFIG_WATCHDOG /* disable the watchdog */
533
wdenkfe8c2802002-11-03 00:38:21 +0000534/*****************************************************************************
535 *
536 * You should not have to modify any of the following settings
537 *
538 *****************************************************************************/
539
540#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
541#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
542#define CONFIG_SACSng 1 /* munged for the SACSng */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500543#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000544
wdenkfe8c2802002-11-03 00:38:21 +0000545/*
546 * Miscellaneous configurable options
547 */
wdenk78137c32003-09-15 18:00:00 +0000548#define CFG_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
wdenk42d1f032003-10-15 23:53:47 +0000549 /* in the bootm command. */
wdenk78137c32003-09-15 18:00:00 +0000550#define CFG_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
wdenk42d1f032003-10-15 23:53:47 +0000551 /* "## <message>" from the bootm cmd */
wdenk78137c32003-09-15 18:00:00 +0000552#define CFG_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
wdenk42d1f032003-10-15 23:53:47 +0000553 /* defined, then the hostname param */
554 /* validated against checkhostname. */
wdenk78137c32003-09-15 18:00:00 +0000555#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
556#define CFG_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
wdenk42d1f032003-10-15 23:53:47 +0000557 /* (limited to maximum of 1024 msec) */
wdenk78137c32003-09-15 18:00:00 +0000558#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
wdenk42d1f032003-10-15 23:53:47 +0000559 /* Check for abort key presses */
560 /* at least once in dependent of the */
561 /* CONFIG_BOOTDELAY value. */
wdenk78137c32003-09-15 18:00:00 +0000562#define CFG_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
563#define CFG_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
wdenk42d1f032003-10-15 23:53:47 +0000564 /* state to the fault LED. */
wdenk78137c32003-09-15 18:00:00 +0000565#define CFG_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
wdenk42d1f032003-10-15 23:53:47 +0000566 /* the Ethernet link state. */
wdenk78137c32003-09-15 18:00:00 +0000567#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
wdenk42d1f032003-10-15 23:53:47 +0000568 /* until the TFTP is successful. */
wdenk78137c32003-09-15 18:00:00 +0000569#define CFG_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
wdenk42d1f032003-10-15 23:53:47 +0000570 /* turn off the STATUS LEDs. */
wdenk78137c32003-09-15 18:00:00 +0000571#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
wdenk42d1f032003-10-15 23:53:47 +0000572 /* incoming data. */
wdenk78137c32003-09-15 18:00:00 +0000573#define CFG_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
wdenk42d1f032003-10-15 23:53:47 +0000574 /* to signify that tftp is moving. */
wdenk78137c32003-09-15 18:00:00 +0000575#define CFG_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
wdenk42d1f032003-10-15 23:53:47 +0000576 /* flash the status LED. */
wdenk78137c32003-09-15 18:00:00 +0000577#define CFG_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
wdenk42d1f032003-10-15 23:53:47 +0000578 /* during the tftp file transfer. */
wdenk78137c32003-09-15 18:00:00 +0000579#define CFG_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
wdenk42d1f032003-10-15 23:53:47 +0000580 /* '#'s from the tftp command. */
wdenk78137c32003-09-15 18:00:00 +0000581#define CFG_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
wdenk42d1f032003-10-15 23:53:47 +0000582 /* issued during the tftp command. */
wdenk78137c32003-09-15 18:00:00 +0000583#define CFG_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
584 /* before it gives up. */
585
Jon Loeliger46da1e92007-07-04 22:33:30 -0500586#if defined(CONFIG_CMD_KGDB)
wdenkfe8c2802002-11-03 00:38:21 +0000587# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
588#else
589# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
590#endif
591
592/* Print Buffer Size */
593#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
594
595#define CFG_MAXARGS 32 /* max number of command args */
596
597#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
598
599#define CFG_LOAD_ADDR 0x400000 /* default load address */
600#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
601
wdenk1d0350e2002-11-11 21:14:20 +0000602#define CFG_ALT_MEMTEST /* Select full-featured memory test */
wdenkfe8c2802002-11-03 00:38:21 +0000603#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
604 /* the exception vector table */
605 /* to the end of the DRAM */
606 /* less monitor and malloc area */
607#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
608#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
609 + CFG_MALLOC_LEN \
610 + CFG_ENV_SECT_SIZE \
611 + CFG_STACK_USAGE )
612
613#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
614 - CFG_MEM_END_USAGE )
615
616/* valid baudrates */
617#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
618
619/*
620 * Low Level Configuration Settings
621 * (address mappings, register initial values, etc.)
622 * You should know what you are doing if you make changes here.
623 */
624
625#define CFG_FLASH_BASE CFG_FLASH0_BASE
626#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
627#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
628#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
629
630/*-----------------------------------------------------------------------
631 * Hard Reset Configuration Words
632 */
633#if defined(CFG_SBC_BOOT_LOW)
634# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
635#else
636# define CFG_SBC_HRCW_BOOT_FLAGS (0)
637#endif /* defined(CFG_SBC_BOOT_LOW) */
638
639/* get the HRCW ISB field from CFG_IMMR */
640#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
641 ((CFG_IMMR & 0x01000000) >> 7) | \
642 ((CFG_IMMR & 0x00100000) >> 4) )
643
644#define CFG_HRCW_MASTER ( HRCW_BPS10 | \
645 HRCW_DPPC11 | \
646 CFG_SBC_HRCW_IMMR | \
647 HRCW_MMR00 | \
648 HRCW_LBPC11 | \
649 HRCW_APPC10 | \
650 HRCW_CS10PC00 | \
651 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
652 CFG_SBC_HRCW_BOOT_FLAGS )
653
654/* no slaves */
655#define CFG_HRCW_SLAVE1 0
656#define CFG_HRCW_SLAVE2 0
657#define CFG_HRCW_SLAVE3 0
658#define CFG_HRCW_SLAVE4 0
659#define CFG_HRCW_SLAVE5 0
660#define CFG_HRCW_SLAVE6 0
661#define CFG_HRCW_SLAVE7 0
662
663/*-----------------------------------------------------------------------
664 * Definitions for initial stack pointer and data area (in DPRAM)
665 */
666#define CFG_INIT_RAM_ADDR CFG_IMMR
667#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
668#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
669#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
670#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
671
672/*-----------------------------------------------------------------------
673 * Start addresses for the final memory configuration
674 * (Set up by the startup code)
675 * Please note that CFG_SDRAM_BASE _must_ start at 0
676 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
677 */
678#define CFG_MONITOR_BASE CFG_FLASH0_BASE
679
680#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
681# define CFG_RAMBOOT
682#endif
683
684#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
685#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
686
687/*
688 * For booting Linux, the board info and command line data
689 * have to be in the first 8 MB of memory, since this is
690 * the maximum mapped by the Linux kernel during initialization.
691 */
692#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
693
694/*-----------------------------------------------------------------------
695 * FLASH and environment organization
696 */
697
698#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
699#undef CFG_FLASH_PROTECTION /* use hardware protection */
700#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
701#define CFG_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
702
703#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
704#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
705
706#ifndef CFG_RAMBOOT
707# define CFG_ENV_IS_IN_FLASH 1
708
709# ifdef CFG_ENV_IN_OWN_SECT
710# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
711# define CFG_ENV_SECT_SIZE 0x10000
712# else
713# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
714# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
715# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
716# endif /* CFG_ENV_IN_OWN_SECT */
717
718#else
719# define CFG_ENV_IS_IN_NVRAM 1
720# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
721# define CFG_ENV_SIZE 0x200
722#endif /* CFG_RAMBOOT */
723
724/*-----------------------------------------------------------------------
725 * Cache Configuration
726 */
727#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
728
Jon Loeliger46da1e92007-07-04 22:33:30 -0500729#if defined(CONFIG_CMD_KGDB)
wdenkfe8c2802002-11-03 00:38:21 +0000730# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
731#endif
732
733/*-----------------------------------------------------------------------
734 * HIDx - Hardware Implementation-dependent Registers 2-11
735 *-----------------------------------------------------------------------
736 * HID0 also contains cache control - initially enable both caches and
737 * invalidate contents, then the final state leaves only the instruction
738 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
739 * but Soft reset does not.
740 *
741 * HID1 has only read-only information - nothing to set.
742 */
743#define CFG_HID0_INIT (HID0_ICE |\
744 HID0_DCE |\
745 HID0_ICFI |\
746 HID0_DCI |\
747 HID0_IFEM |\
748 HID0_ABE)
749
750#define CFG_HID0_FINAL (HID0_ICE |\
751 HID0_IFEM |\
752 HID0_ABE |\
753 HID0_EMCP)
754#define CFG_HID2 0
755
756/*-----------------------------------------------------------------------
757 * RMR - Reset Mode Register
758 *-----------------------------------------------------------------------
759 */
760#define CFG_RMR 0
761
762/*-----------------------------------------------------------------------
763 * BCR - Bus Configuration 4-25
764 *-----------------------------------------------------------------------
765 */
766#define CFG_BCR (BCR_ETM)
767
768/*-----------------------------------------------------------------------
769 * SIUMCR - SIU Module Configuration 4-31
770 *-----------------------------------------------------------------------
771 */
772
773#define CFG_SIUMCR (SIUMCR_DPPC11 |\
774 SIUMCR_L2CPC00 |\
775 SIUMCR_APPC10 |\
776 SIUMCR_MMR00)
777
778
779/*-----------------------------------------------------------------------
780 * SYPCR - System Protection Control 11-9
781 * SYPCR can only be written once after reset!
782 *-----------------------------------------------------------------------
783 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
784 */
wdenk78137c32003-09-15 18:00:00 +0000785#if defined(CONFIG_WATCHDOG)
786#define CFG_SYPCR (SYPCR_SWTC |\
787 SYPCR_BMT |\
788 SYPCR_PBME |\
789 SYPCR_LBME |\
790 SYPCR_SWRI |\
791 SYPCR_SWP |\
wdenk42d1f032003-10-15 23:53:47 +0000792 SYPCR_SWE)
wdenk78137c32003-09-15 18:00:00 +0000793#else
wdenkfe8c2802002-11-03 00:38:21 +0000794#define CFG_SYPCR (SYPCR_SWTC |\
795 SYPCR_BMT |\
796 SYPCR_PBME |\
797 SYPCR_LBME |\
798 SYPCR_SWRI |\
799 SYPCR_SWP)
wdenk78137c32003-09-15 18:00:00 +0000800#endif /* CONFIG_WATCHDOG */
wdenkfe8c2802002-11-03 00:38:21 +0000801
802/*-----------------------------------------------------------------------
803 * TMCNTSC - Time Counter Status and Control 4-40
804 *-----------------------------------------------------------------------
805 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
806 * and enable Time Counter
807 */
808#define CFG_TMCNTSC (TMCNTSC_SEC |\
809 TMCNTSC_ALR |\
810 TMCNTSC_TCF |\
811 TMCNTSC_TCE)
812
813/*-----------------------------------------------------------------------
814 * PISCR - Periodic Interrupt Status and Control 4-42
815 *-----------------------------------------------------------------------
816 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
817 * Periodic timer
818 */
819#define CFG_PISCR (PISCR_PS |\
820 PISCR_PTF |\
821 PISCR_PTE)
822
823/*-----------------------------------------------------------------------
824 * SCCR - System Clock Control 9-8
825 *-----------------------------------------------------------------------
826 */
827#define CFG_SCCR 0
828
829/*-----------------------------------------------------------------------
830 * RCCR - RISC Controller Configuration 13-7
831 *-----------------------------------------------------------------------
832 */
833#define CFG_RCCR 0
834
835/*
836 * Initialize Memory Controller:
837 *
838 * Bank Bus Machine PortSz Device
839 * ---- --- ------- ------ ------
840 * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
841 * 1 60x GPCM -- bit (Unused)
842 * 2 60x SDRAM 64 bit SDRAM (DIMM)
843 * 3 60x SDRAM 64 bit SDRAM (DIMM)
844 * 4 60x GPCM -- bit (Unused)
845 * 5 60x GPCM -- bit (Unused)
846 * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
847 */
848
849/*-----------------------------------------------------------------------
850 * BR0,BR1 - Base Register
851 * Ref: Section 10.3.1 on page 10-14
852 * OR0,OR1 - Option Register
853 * Ref: Section 10.3.2 on page 10-18
854 *-----------------------------------------------------------------------
855 */
856
857/* Bank 0 - Primary FLASH
858 */
859
860/* BR0 is configured as follows:
861 *
862 * - Base address of 0x40000000
863 * - 16 bit port size
864 * - Data errors checking is disabled
865 * - Read and write access
866 * - GPCM 60x bus
867 * - Access are handled by the memory controller according to MSEL
868 * - Not used for atomic operations
869 * - No data pipelining is done
870 * - Valid
871 */
872#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
873 BRx_PS_16 |\
874 BRx_MS_GPCM_P |\
875 BRx_V)
876
877/* OR0 is configured as follows:
878 *
879 * - 4 MB
880 * - *BCTL0 is asserted upon access to the current memory bank
881 * - *CW / *WE are negated a quarter of a clock earlier
882 * - *CS is output at the same time as the address lines
883 * - Uses a clock cycle length of 5
884 * - *PSDVAL is generated internally by the memory controller
885 * unless *GTA is asserted earlier externally.
886 * - Relaxed timing is generated by the GPCM for accesses
887 * initiated to this memory region.
888 * - One idle clock is inserted between a read access from the
889 * current bank and the next access.
890 */
891#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
892 ORxG_CSNT |\
893 ORxG_ACS_DIV1 |\
894 ORxG_SCY_5_CLK |\
895 ORxG_TRLX |\
896 ORxG_EHTR)
897
898/*-----------------------------------------------------------------------
899 * BR2,BR3 - Base Register
900 * Ref: Section 10.3.1 on page 10-14
901 * OR2,OR3 - Option Register
902 * Ref: Section 10.3.2 on page 10-16
903 *-----------------------------------------------------------------------
904 */
905
906/* Bank 2,3 - SDRAM DIMM
907 */
908
909/* The BR2 is configured as follows:
910 *
911 * - Base address of 0x00000000
912 * - 64 bit port size (60x bus only)
913 * - Data errors checking is disabled
914 * - Read and write access
915 * - SDRAM 60x bus
916 * - Access are handled by the memory controller according to MSEL
917 * - Not used for atomic operations
918 * - No data pipelining is done
919 * - Valid
920 */
921#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
922 BRx_PS_64 |\
923 BRx_MS_SDRAM_P |\
924 BRx_V)
925
926#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
927 BRx_PS_64 |\
928 BRx_MS_SDRAM_P |\
929 BRx_V)
930
931/* With a 64 MB DIMM, the OR2 is configured as follows:
932 *
933 * - 64 MB
934 * - 4 internal banks per device
935 * - Row start address bit is A8 with PSDMR[PBI] = 0
936 * - 12 row address lines
937 * - Back-to-back page mode
938 * - Internal bank interleaving within save device enabled
939 */
940#if (CFG_SDRAM0_SIZE == 64)
941#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
942 ORxS_BPD_4 |\
943 ORxS_ROWST_PBI0_A8 |\
944 ORxS_NUMR_12)
945#else
946#error "INVALID SDRAM CONFIGURATION"
947#endif
948
949/*-----------------------------------------------------------------------
950 * PSDMR - 60x Bus SDRAM Mode Register
951 * Ref: Section 10.3.3 on page 10-21
952 *-----------------------------------------------------------------------
953 */
954
955/* Address that the DIMM SPD memory lives at.
956 */
957#define SDRAM_SPD_ADDR 0x50
958
959#if (CFG_SDRAM0_SIZE == 64)
960/* With a 64 MB DIMM, the PSDMR is configured as follows:
961 *
962 * - Bank Based Interleaving,
963 * - Refresh Enable,
964 * - Address Multiplexing where A5 is output on A14 pin
965 * (A6 on A15, and so on),
966 * - use address pins A14-A16 as bank select,
967 * - A9 is output on SDA10 during an ACTIVATE command,
968 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
969 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
970 * is 3 clocks,
971 * - earliest timing for READ/WRITE command after ACTIVATE command is
972 * 2 clocks,
973 * - earliest timing for PRECHARGE after last data was read is 1 clock,
974 * - earliest timing for PRECHARGE after last data was written is 1 clock,
975 * - CAS Latency is 2.
976 */
977#define CFG_PSDMR (PSDMR_RFEN |\
978 PSDMR_SDAM_A14_IS_A5 |\
979 PSDMR_BSMA_A14_A16 |\
980 PSDMR_SDA10_PBI0_A9 |\
981 PSDMR_RFRC_7_CLK |\
982 PSDMR_PRETOACT_3W |\
983 PSDMR_ACTTORW_2W |\
984 PSDMR_LDOTOPRE_1C |\
985 PSDMR_WRC_1C |\
986 PSDMR_CL_2)
987#else
988#error "INVALID SDRAM CONFIGURATION"
989#endif
990
991/*
992 * Shoot for approximately 1MHz on the prescaler.
993 */
994#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
995#define CFG_MPTPR MPTPR_PTP_DIV64
996#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
997#define CFG_MPTPR MPTPR_PTP_DIV32
998#else
999#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
1000#define CFG_MPTPR MPTPR_PTP_DIV32
1001#endif
1002#define CFG_PSRT 14
1003
1004
1005/*-----------------------------------------------------------------------
1006 * BR6 - Base Register
1007 * Ref: Section 10.3.1 on page 10-14
1008 * OR6 - Option Register
1009 * Ref: Section 10.3.2 on page 10-18
1010 *-----------------------------------------------------------------------
1011 */
1012
1013/* Bank 6 - Secondary FLASH
1014 *
1015 * The secondary FLASH is connected to *CS6
1016 */
1017#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
1018
1019/* BR6 is configured as follows:
1020 *
1021 * - Base address of 0x60000000
1022 * - 16 bit port size
1023 * - Data errors checking is disabled
1024 * - Read and write access
1025 * - GPCM 60x bus
1026 * - Access are handled by the memory controller according to MSEL
1027 * - Not used for atomic operations
1028 * - No data pipelining is done
1029 * - Valid
1030 */
1031# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
1032 BRx_PS_16 |\
1033 BRx_MS_GPCM_P |\
1034 BRx_V)
1035
1036/* OR6 is configured as follows:
1037 *
1038 * - 2 MB
1039 * - *BCTL0 is asserted upon access to the current memory bank
1040 * - *CW / *WE are negated a quarter of a clock earlier
1041 * - *CS is output at the same time as the address lines
1042 * - Uses a clock cycle length of 5
1043 * - *PSDVAL is generated internally by the memory controller
1044 * unless *GTA is asserted earlier externally.
1045 * - Relaxed timing is generated by the GPCM for accesses
1046 * initiated to this memory region.
1047 * - One idle clock is inserted between a read access from the
1048 * current bank and the next access.
1049 */
1050# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
1051 ORxG_CSNT |\
1052 ORxG_ACS_DIV1 |\
1053 ORxG_SCY_5_CLK |\
1054 ORxG_TRLX |\
1055 ORxG_EHTR)
1056#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
1057
1058/*
1059 * Internal Definitions
1060 *
1061 * Boot Flags
1062 */
1063#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1064#define BOOTFLAG_WARM 0x02 /* Software reboot */
1065
1066#endif /* __CONFIG_H */