blob: dc07d3df0636a30e771334c103adf9074b361374 [file] [log] [blame]
Wolfgang Denk4ff170a2008-07-03 22:34:08 +02001#include <common.h>
wdenkd1cbe852003-06-28 17:24:46 +00002#include <asm/u-boot.h>
3#include <asm/processor.h>
wdenkd1cbe852003-06-28 17:24:46 +00004#include "exbitgen.h"
5
Stefan Roesebbeff302008-06-02 17:37:28 +02006void sdram_init(void);
7
wdenkd1cbe852003-06-28 17:24:46 +00008/* ************************************************************************ */
wdenkc837dcb2004-01-20 23:12:12 +00009int board_early_init_f (void)
wdenkd1cbe852003-06-28 17:24:46 +000010/* ------------------------------------------------------------------------ --
11 * Purpose :
12 * Remarks :
13 * Restrictions:
14 * See also :
15 * Example :
16 * ************************************************************************ */
17{
18 unsigned long i;
19
20 /*-------------------------------------------------------------------------+
21 | Interrupt controller setup for the Walnut board.
22 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
23 | IRQ 16 405GP internally generated; active low; level sensitive
24 | IRQ 17-24 RESERVED
25 | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
26 | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
27 | IRQ 27 (EXT IRQ 2) Not Used
28 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
29 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
30 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
31 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
32 | Note for Walnut board:
33 | An interrupt taken for the FPGA (IRQ 25) indicates that either
34 | the Mouse, Keyboard, IRDA, or External Expansion caused the
35 | interrupt. The FPGA must be read to determine which device
36 | caused the interrupt. The default setting of the FPGA clears
37 |
38 +-------------------------------------------------------------------------*/
39
40 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
41 mtdcr (uicer, 0x00000000); /* disable all ints */
42 mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
43 mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */
44 mtdcr (uictr, 0x10000000); /* set int trigger levels */
45 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
46 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
47
48 /* Perform reset of PHY connected to PPC via register in CPLD */
49 out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */
50 for (i = 0; i < 10000000; i++) {
51 ;
52 }
53 out8 (PHY_CTRL_ADDR, 0x2f); /* deactivate nRESET */
54
55 return 0;
56}
57
58
59/* ************************************************************************ */
60int checkboard (void)
61/* ------------------------------------------------------------------------ --
62 * Purpose :
63 * Remarks :
64 * Restrictions:
65 * See also :
66 * Example :
67 * ************************************************************************ */
68{
69 printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR));
70 return (0);
71}
72
73/* ************************************************************************ */
Becky Bruce9973e3c2008-06-09 16:03:40 -050074phys_size_t initdram (int board_type)
wdenkd1cbe852003-06-28 17:24:46 +000075/* ------------------------------------------------------------------------ --
76 * Purpose : Determines size of mounted DRAM.
77 * Remarks : Size is determined by reading SDRAM configuration registers as
78 * set up by sdram_init.
79 * Restrictions:
80 * See also :
81 * Example :
82 * ************************************************************************ */
83{
84 ulong tot_size;
85 ulong bank_size;
86 ulong tmp;
87
Stefan Roesebbeff302008-06-02 17:37:28 +020088 /*
89 * ToDo: Move the asm init routine sdram_init() to this C file,
90 * or even better use some common ppc4xx code available
91 * in cpu/ppc4xx
92 */
93 sdram_init();
94
wdenkd1cbe852003-06-28 17:24:46 +000095 tot_size = 0;
96
97 mtdcr (memcfga, mem_mb0cf);
98 tmp = mfdcr (memcfgd);
99 if (tmp & 0x00000001) {
100 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
101 tot_size += bank_size;
102 }
103
104 mtdcr (memcfga, mem_mb1cf);
105 tmp = mfdcr (memcfgd);
106 if (tmp & 0x00000001) {
107 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
108 tot_size += bank_size;
109 }
110
111 mtdcr (memcfga, mem_mb2cf);
112 tmp = mfdcr (memcfgd);
113 if (tmp & 0x00000001) {
114 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
115 tot_size += bank_size;
116 }
117
118 mtdcr (memcfga, mem_mb3cf);
119 tmp = mfdcr (memcfgd);
120 if (tmp & 0x00000001) {
121 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
122 tot_size += bank_size;
123 }
124
125 return tot_size;
126}