Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0+ |
Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 2 | # |
| 3 | # Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 4 | |
| 5 | if VENDOR_INTEL |
| 6 | |
| 7 | choice |
| 8 | prompt "Mainboard model" |
Joe Hershberger | a26cd04 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 9 | optional |
Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 10 | |
Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 11 | config TARGET_BAYLEYBAY |
| 12 | bool "Bayley Bay" |
| 13 | help |
| 14 | This is the Intel Bayley Bay Customer Reference Board. It contains an |
| 15 | Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM |
| 16 | 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC, |
| 17 | PCIe and some other sensor interfaces. |
| 18 | |
Bin Meng | eb45787 | 2017-08-15 22:42:02 -0700 | [diff] [blame] | 19 | config TARGET_CHERRYHILL |
| 20 | bool "Cherry Hill" |
| 21 | help |
| 22 | This is the Intel Cherry Hill Customer Reference Board. It is in a |
| 23 | mini-ITX form factor containing the Intel Braswell SoC, which has |
| 24 | a 64-bit quad-core, single-thread, Intel Atom processor, along with |
| 25 | serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe, |
| 26 | some GPIOs, one HDMI and two DP video out. |
| 27 | |
Bin Meng | a2e3b05 | 2016-02-17 00:16:25 -0800 | [diff] [blame] | 28 | config TARGET_COUGARCANYON2 |
| 29 | bool "Cougar Canyon 2" |
| 30 | help |
| 31 | This is the Intel Cougar Canyon 2 Customer Reference Board. It |
| 32 | is built on the Chief River platform with Intel Ivybridge Processor |
| 33 | and Panther Point chipset. The board has 4GB RAM, with some other |
| 34 | peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI. |
| 35 | |
Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 36 | config TARGET_CROWNBAY |
| 37 | bool "Crown Bay" |
| 38 | help |
| 39 | This is the Intel Crown Bay Customer Reference Board. It contains |
| 40 | the Intel Atom Processor E6xx populated on the COM Express module |
| 41 | with 1GB DDR2 soldered down memory and a carrier board with the |
| 42 | Intel Platform Controller Hub EG20T, other system components and |
| 43 | peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. |
| 44 | |
Andy Shevchenko | 495f377 | 2017-07-06 14:41:53 +0300 | [diff] [blame] | 45 | config TARGET_EDISON |
| 46 | bool "Edison" |
| 47 | help |
| 48 | This is the Intel Edison Compute Module. It contains a dual core Intel |
| 49 | Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB |
| 50 | eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers. |
| 51 | |
Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 52 | config TARGET_GALILEO |
| 53 | bool "Galileo" |
| 54 | help |
| 55 | This is the Intel Galileo board, which is the first in a family of |
| 56 | Arduino-certified development and prototyping boards based on Intel |
| 57 | architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit |
| 58 | single-core, single-thread, Intel Pentium processor instrunction set |
| 59 | architecture (ISA) compatible, operating at speeds up to 400Mhz, |
| 60 | along with 256MB DDR3 memory. It supports a wide range of industry |
| 61 | standard I/O interfaces, including a full-sized mini-PCIe slot, |
| 62 | one 100Mb Ethernet port, a microSD card slot, a USB host port and |
| 63 | a USB client port. |
| 64 | |
| 65 | config TARGET_MINNOWMAX |
| 66 | bool "Minnowboard MAX" |
| 67 | help |
| 68 | This is the Intel Minnowboard MAX. It contains an Atom E3800 |
| 69 | processor in a small form factor with Ethernet, micro-SD, USB 2, |
| 70 | USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. |
| 71 | It requires some binary blobs - see README.x86 for details. |
| 72 | |
| 73 | Note that PCIE_ECAM_BASE is set up by the FSP so the value used |
| 74 | by U-Boot matches that value. |
| 75 | |
Park, Aiden | d8f6db4 | 2019-08-03 08:31:11 +0000 | [diff] [blame] | 76 | config TARGET_SLIMBOOTLOADER |
| 77 | bool "slimbootloader" |
| 78 | help |
| 79 | This target is used for running U-Boot on top of Slim Bootloader |
| 80 | boot firmware as a payload. Slim Bootloader does memory initialization |
| 81 | and silicon initialization, and it passes necessary information in |
| 82 | HOB (Hand Off Block) to a payload. The payload consumes HOB data |
| 83 | which is generated by Slim Bootloader for its driver initialization. |
| 84 | Slim Bootloader consumes FSP and its HOB, but FSP HOB is cleared |
| 85 | Before launching a payload. Instead, Slim Bootloader generates its |
| 86 | HOB data such as memory info, serial port info and so on. |
| 87 | Refer to doc/board/intel/slimbootloader.rst for the details. |
| 88 | |
Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 89 | endchoice |
| 90 | |
Bin Meng | 9b911be | 2015-07-30 03:49:17 -0700 | [diff] [blame] | 91 | source "board/intel/bayleybay/Kconfig" |
Bin Meng | eb45787 | 2017-08-15 22:42:02 -0700 | [diff] [blame] | 92 | source "board/intel/cherryhill/Kconfig" |
Bin Meng | a2e3b05 | 2016-02-17 00:16:25 -0800 | [diff] [blame] | 93 | source "board/intel/cougarcanyon2/Kconfig" |
Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 94 | source "board/intel/crownbay/Kconfig" |
Andy Shevchenko | 495f377 | 2017-07-06 14:41:53 +0300 | [diff] [blame] | 95 | source "board/intel/edison/Kconfig" |
Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 96 | source "board/intel/galileo/Kconfig" |
| 97 | source "board/intel/minnowmax/Kconfig" |
Park, Aiden | d8f6db4 | 2019-08-03 08:31:11 +0000 | [diff] [blame] | 98 | source "board/intel/slimbootloader/Kconfig" |
Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 99 | |
| 100 | endif |