blob: 414360fe4793e33b1a3972fa655ecb8228536af6 [file] [log] [blame]
liu haoe3aafef2019-10-31 07:51:08 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019
4 * shuyiqi <shuyiqi@phytium.com.cn>
5 * liuhao <liuhao@phytium.com.cn>
6 */
7
8#include <common.h>
Simon Glass09140112020-05-10 11:40:03 -06009#include <command.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -070010#include <cpu_func.h>
Simon Glass691d7192020-05-10 11:40:02 -060011#include <init.h>
liu haoe3aafef2019-10-31 07:51:08 +000012#include <asm/armv8/mmu.h>
Simon Glass90526e92020-05-10 11:39:56 -060013#include <asm/cache.h>
liu haoe3aafef2019-10-31 07:51:08 +000014#include <asm/system.h>
15#include <asm/io.h>
16#include <linux/arm-smccc.h>
17#include <linux/kernel.h>
18#include <scsi.h>
19#include "cpu.h"
20
21DECLARE_GLOBAL_DATA_PTR;
22
23int dram_init(void)
24{
25 gd->mem_clk = 0;
26 gd->ram_size = PHYS_SDRAM_1_SIZE;
27 return 0;
28}
29
30int dram_init_banksize(void)
31{
32 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
33 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
34
35 return 0;
36}
37
38int board_init(void)
39{
40 return 0;
41}
42
43void reset_cpu(ulong addr)
44{
45 struct arm_smccc_res res;
46
47 arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
48 debug("reset cpu error, %lx\n", res.a0);
49}
50
51static struct mm_region durian_mem_map[] = {
52 {
53 .virt = 0x0UL,
54 .phys = 0x0UL,
55 .size = 0x80000000UL,
56 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
57 PTE_BLOCK_NON_SHARE |
58 PTE_BLOCK_PXN |
59 PTE_BLOCK_UXN
60 },
61 {
62 .virt = (u64)PHYS_SDRAM_1,
63 .phys = (u64)PHYS_SDRAM_1,
64 .size = (u64)PHYS_SDRAM_1_SIZE,
65 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
66 PTE_BLOCK_NS |
67 PTE_BLOCK_INNER_SHARE
68 },
69 {
70 0,
71 }
72};
73
74struct mm_region *mem_map = durian_mem_map;
75
76int print_cpuinfo(void)
77{
78 printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
79 return 0;
80}
81
82int __asm_flush_l3_dcache(void)
83{
84 int i, pstate;
85
86 for (i = 0; i < HNF_COUNT; i++)
87 writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
88 for (i = 0; i < HNF_COUNT; i++) {
89 do {
90 pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
91 } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
92 }
93
94 for (i = 0; i < HNF_COUNT; i++)
95 writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
96
97 return 0;
98}
99
100int last_stage_init(void)
101{
102 int ret;
103
104 /* pci e */
105 pci_init();
106 /* scsi scan */
107 ret = scsi_scan(true);
108 if (ret) {
109 printf("scsi scan failed\n");
110 return CMD_RET_FAILURE;
111 }
112 return ret;
113}
114