blob: a42910f60001281dcea0ac371a067097054dc89e [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Fleming87e29872015-11-04 15:48:32 -06002/*
3 * Based on corenet_ds.c
Andy Fleming87e29872015-11-04 15:48:32 -06004 */
5
6#include <common.h>
7#include <command.h>
Simon Glass7b51b572019-08-01 09:46:52 -06008#include <env.h>
Simon Glass807765b2019-12-28 10:44:54 -07009#include <fdt_support.h>
Simon Glass4d72caa2020-05-10 11:40:01 -060010#include <image.h>
Simon Glass52559322019-11-14 12:57:46 -070011#include <init.h>
Andy Fleming87e29872015-11-04 15:48:32 -060012#include <netdev.h>
13#include <linux/compiler.h>
14#include <asm/mmu.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17#include <asm/immap_85xx.h>
18#include <asm/fsl_law.h>
19#include <asm/fsl_serdes.h>
20#include <asm/fsl_portals.h>
21#include <asm/fsl_liodn.h>
22#include <fm_eth.h>
23#include <pci.h>
24
25#include "cyrus.h"
26#include "../common/eeprom.h"
27
Andy Fleming87e29872015-11-04 15:48:32 -060028#define GPIO_OPENDRAIN 0x30000000
29#define GPIO_DIR 0x3c000004
30#define GPIO_INITIAL 0x30000000
31#define GPIO_VGA_SWITCH 0x00001000
32
33int checkboard(void)
34{
35 printf("Board: CYRUS\n");
36
37 return 0;
38}
39
40int board_early_init_f(void)
41{
42 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
43 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
44
45 /*
46 * Only use DDR1_MCK0/3 and DDR2_MCK0/3
47 * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
48 * the noise introduced by these unterminated and unused clock pairs.
49 */
50 setbits_be32(&gur->ddrclkdr, 0x001B001B);
51
52 /* Set GPIO reset lines to open-drain, tristate */
53 setbits_be32(&pgpio->gpdat, GPIO_INITIAL);
54 setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN);
55
56 /* Set GPIO Direction */
57 setbits_be32(&pgpio->gpdir, GPIO_DIR);
58
59 return 0;
60}
61
62int board_early_init_r(void)
63{
64 fsl_lbc_t *lbc = LBC_BASE_ADDR;
65
66 out_be32(&lbc->lbcr, 0);
67 /* 1 clock LALE cycle */
68 out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR);
69
70 set_liodns();
71
72#ifdef CONFIG_SYS_DPAA_QBMAN
Ahmed Mansour44262322017-12-15 16:01:00 -050073 setup_qbman_portals();
Andy Fleming87e29872015-11-04 15:48:32 -060074#endif
75 print_lbc_regs();
76 return 0;
77}
78
79int misc_init_r(void)
80{
81 return 0;
82}
83
84int ft_board_setup(void *blob, bd_t *bd)
85{
86 phys_addr_t base;
87 phys_size_t size;
88
89 ft_cpu_setup(blob, bd);
90
Simon Glass723806c2017-08-03 12:22:15 -060091 base = env_get_bootm_low();
92 size = env_get_bootm_size();
Andy Fleming87e29872015-11-04 15:48:32 -060093
94 fdt_fixup_memory(blob, (u64)base, (u64)size);
95
96#ifdef CONFIG_PCI
97 pci_of_setup(blob, bd);
98#endif
99
100 fdt_fixup_liodn(blob);
Sriram Dasha5c289b2016-09-16 17:12:15 +0530101 fsl_fdt_fixup_dr_usb(blob, bd);
Andy Fleming87e29872015-11-04 15:48:32 -0600102
103#ifdef CONFIG_SYS_DPAA_FMAN
104 fdt_fixup_fman_ethernet(blob);
105#endif
106
107 return 0;
108}
109
110int mac_read_from_eeprom(void)
111{
112 init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM,
113 CONFIG_SYS_I2C_EEPROM_ADDR,
114 CONFIG_SYS_I2C_EEPROM_ADDR_LEN);
115
116 return mac_read_from_eeprom_common();
117}