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Yusuke Godac133c1f2008-03-11 12:55:12 +09001/*
2 * Configuation settings for the Renesas R7780MP board
3 *
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +09004 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yusuke Godac133c1f2008-03-11 12:55:12 +09005 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Yusuke Godac133c1f2008-03-11 12:55:12 +09008 */
9
10#ifndef __R7780RP_H
11#define __R7780RP_H
12
Yusuke Godac133c1f2008-03-11 12:55:12 +090013#define CONFIG_CPU_SH7780 1
14#define CONFIG_R7780MP 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020015#define CONFIG_SYS_R7780MP_OLD_FLASH 1
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090016#define __LITTLE_ENDIAN__ 1
Yusuke Godac133c1f2008-03-11 12:55:12 +090017
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020018#define CONFIG_DISPLAY_BOARDINFO
19
Yusuke Godac133c1f2008-03-11 12:55:12 +090020/*
21 * Command line configuration.
22 */
23#define CONFIG_CMD_SDRAM
Yusuke Godac133c1f2008-03-11 12:55:12 +090024#define CONFIG_CMD_PCI
Yusuke Godac133c1f2008-03-11 12:55:12 +090025#define CONFIG_CMD_IDE
Yusuke Godac133c1f2008-03-11 12:55:12 +090026
Jean-Christophe PLAGNIOL-VILLARD6c58a032008-08-13 01:40:38 +020027#define CONFIG_SCIF_CONSOLE 1
Yusuke Godac133c1f2008-03-11 12:55:12 +090028#define CONFIG_CONS_SCIF0 1
29
Yusuke Godac133c1f2008-03-11 12:55:12 +090030#define CONFIG_BOOTARGS "console=ttySC0,115200"
31#define CONFIG_ENV_OVERWRITE 1
32
Nobuhiro Iwamatsu913c8912011-01-17 20:50:26 +090033#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_SDRAM_BASE (0x08000000)
35#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090036
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_LONGHELP
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_CBSIZE 256
39#define CONFIG_SYS_PBSIZE 256
40#define CONFIG_SYS_MAXARGS 16
41#define CONFIG_SYS_BARGSIZE 512
Yusuke Godac133c1f2008-03-11 12:55:12 +090042
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +020044#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Yusuke Godac133c1f2008-03-11 12:55:12 +090045
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090046/* Flash board support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_FLASH_BASE (0xA0000000)
48#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090049/* NOR Flash (S29PL127J60TFI130) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
51# define CONFIG_SYS_MAX_FLASH_BANKS (2)
52# define CONFIG_SYS_MAX_FLASH_SECT 270
53# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
54 CONFIG_SYS_FLASH_BASE + 0x100000,\
55 CONFIG_SYS_FLASH_BASE + 0x400000,\
56 CONFIG_SYS_FLASH_BASE + 0x700000, }
57#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090058/* NOR Flash (Spantion S29GL256P) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059# define CONFIG_SYS_MAX_FLASH_BANKS (1)
60# define CONFIG_SYS_MAX_FLASH_SECT 256
61# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
62#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
Yusuke Godac133c1f2008-03-11 12:55:12 +090063
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090065/* Address of u-boot image in Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
67#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090068/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090070
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
72#define CONFIG_SYS_RX_ETH_BUFFER (8)
Yusuke Godac133c1f2008-03-11 12:55:12 +090073
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020075#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
77#undef CONFIG_SYS_FLASH_QUIET_TEST
Yusuke Godac133c1f2008-03-11 12:55:12 +090078/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_FLASH_EMPTY_INFO
Yusuke Godac133c1f2008-03-11 12:55:12 +090080
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020081#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020082#define CONFIG_ENV_SECT_SIZE (256 * 1024)
83#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
85#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
86#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Yusuke Godac133c1f2008-03-11 12:55:12 +090087
88/* Board Clock */
89#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090090#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
91#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020092#define CONFIG_SYS_TMU_CLK_DIV 4
Yusuke Godac133c1f2008-03-11 12:55:12 +090093
94/* PCI Controller */
95#if defined(CONFIG_CMD_PCI)
Yusuke Godac133c1f2008-03-11 12:55:12 +090096#define CONFIG_SH4_PCI
Nobuhiro Iwamatsuab8f4d42008-03-24 02:11:26 +090097#define CONFIG_SH7780_PCI
Yoshihiro Shimoda06b18162009-02-25 14:26:42 +090098#define CONFIG_SH7780_PCI_LSR 0x07f00001
99#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
100#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
Yusuke Godac133c1f2008-03-11 12:55:12 +0900101#define CONFIG_PCI_SCAN_SHOW 1
Yusuke Godac133c1f2008-03-11 12:55:12 +0900102#define __mem_pci
103
104#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
105#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
106#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
107
108#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
109#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
110#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
Nobuhiro Iwamatsu04366d02009-07-08 11:42:19 +0900111#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
112#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
113#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
Yusuke Godac133c1f2008-03-11 12:55:12 +0900114#endif /* CONFIG_CMD_PCI */
115
116#if defined(CONFIG_CMD_NET)
Marcel Ziswilerc7c1dbb2009-09-09 21:09:00 +0200117/* AX88796L Support(NE2000 base chip) */
Yusuke Godac133c1f2008-03-11 12:55:12 +0900118#define CONFIG_DRIVER_AX88796L
119#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
120#endif
121
122/* Compact flash Support */
123#if defined(CONFIG_CMD_IDE)
124#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_PIO_MODE 1
126#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
127#define CONFIG_SYS_IDE_MAXDEVICE 1
128#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
129#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
130#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
131#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
132#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
Albert Aribaudf2a37fc2010-08-08 05:17:05 +0530133#define CONFIG_IDE_SWAP_IO
Yusuke Godac133c1f2008-03-11 12:55:12 +0900134#endif /* CONFIG_CMD_IDE */
135
136#endif /* __R7780RP_H */