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Bo Shen3225f342013-05-12 22:40:54 +00001/*
2 * Configuation settings for the SAMA5D3xEK board.
3 *
4 * Copyright (C) 2012 - 2013 Atmel
5 *
6 * based on at91sam9m10g45ek.h by:
7 * Stelian Pop <stelian@popies.net>
8 * Lead Tech Design <www.leadtechdesign.com>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Bo Shen3225f342013-05-12 22:40:54 +000011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Wu, Joshb2d387b2015-03-30 14:51:19 +080016#include "at91-sama5_common.h"
Bo Shen3225f342013-05-12 22:40:54 +000017
Wu, Josh89a36582015-08-19 19:11:19 +080018#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
19
Bo Shen3225f342013-05-12 22:40:54 +000020/*
21 * This needs to be defined for the OHCI code to work but it is defined as
22 * ATMEL_ID_UHPHS in the CPU specific header files.
23 */
24#define ATMEL_ID_UHP ATMEL_ID_UHPHS
25
26/*
27 * Specify the clock enable bit in the PMC_SCER register.
28 */
29#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
30
31/* LCD */
Bo Shen3225f342013-05-12 22:40:54 +000032#define LCD_BPP LCD_COLOR16
33#define LCD_OUTPUT_BPP 24
34#define CONFIG_LCD_LOGO
Bo Shen3225f342013-05-12 22:40:54 +000035#define CONFIG_LCD_INFO
36#define CONFIG_LCD_INFO_BELOW_LOGO
Bo Shen3225f342013-05-12 22:40:54 +000037#define CONFIG_ATMEL_HLCD
38#define CONFIG_ATMEL_LCD_RGB565
Bo Shen3225f342013-05-12 22:40:54 +000039
40/* board specific (not enough SRAM) */
41#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
42
Bo Shend6b79432014-07-18 16:43:08 +080043/* NOR flash */
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090044#ifdef CONFIG_MTD_NOR_FLASH
Bo Shend6b79432014-07-18 16:43:08 +080045#define CONFIG_FLASH_CFI_DRIVER
46#define CONFIG_SYS_FLASH_CFI
47#define CONFIG_SYS_FLASH_PROTECTION
48#define CONFIG_SYS_FLASH_BASE 0x10000000
49#define CONFIG_SYS_MAX_FLASH_SECT 131
50#define CONFIG_SYS_MAX_FLASH_BANKS 1
Bo Shend6b79432014-07-18 16:43:08 +080051#endif
Bo Shen3225f342013-05-12 22:40:54 +000052
Bo Shen3225f342013-05-12 22:40:54 +000053/* SDRAM */
54#define CONFIG_NR_DRAM_BANKS 1
55#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
56#define CONFIG_SYS_SDRAM_SIZE 0x20000000
57
Bo Shenc5e88852013-11-15 11:12:38 +080058#ifdef CONFIG_SPL_BUILD
Wenyou Yanga97cb062017-04-14 08:51:42 +080059#define CONFIG_SYS_INIT_SP_ADDR 0x318000
Bo Shenc5e88852013-11-15 11:12:38 +080060#else
Bo Shen3225f342013-05-12 22:40:54 +000061#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yanga97cb062017-04-14 08:51:42 +080062 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shenc5e88852013-11-15 11:12:38 +080063#endif
Bo Shen3225f342013-05-12 22:40:54 +000064
65/* SerialFlash */
Bo Shen3225f342013-05-12 22:40:54 +000066
67#ifdef CONFIG_CMD_SF
Bo Shen3225f342013-05-12 22:40:54 +000068#define CONFIG_SF_DEFAULT_SPEED 30000000
69#endif
70
71/* NAND flash */
72#define CONFIG_CMD_NAND
73
74#ifdef CONFIG_CMD_NAND
Bo Shen3225f342013-05-12 22:40:54 +000075#define CONFIG_NAND_ATMEL
76#define CONFIG_SYS_MAX_NAND_DEVICE 1
77#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
78/* our ALE is AD21 */
79#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
80/* our CLE is AD22 */
81#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
82#define CONFIG_SYS_NAND_ONFI_DETECTION
83/* PMECC & PMERRLOC */
84#define CONFIG_ATMEL_NAND_HWECC
85#define CONFIG_ATMEL_NAND_HW_PMECC
86#define CONFIG_PMECC_CAP 4
87#define CONFIG_PMECC_SECTOR_SIZE 512
Bo Shen3225f342013-05-12 22:40:54 +000088#define CONFIG_CMD_NAND_TRIMFFS
89#endif
90
Bo Shene08d6f32013-06-26 10:11:06 +080091#define CONFIG_PHY_MICREL_KSZ9021
Bo Shen3225f342013-05-12 22:40:54 +000092
Bo Shen3225f342013-05-12 22:40:54 +000093/* USB */
Bo Shen3225f342013-05-12 22:40:54 +000094
95#ifdef CONFIG_CMD_USB
Bo Shendcd2f1a2013-10-21 16:14:00 +080096#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Bo Shen3225f342013-05-12 22:40:54 +000097#define CONFIG_USB_OHCI_NEW
98#define CONFIG_SYS_USB_OHCI_CPU_INIT
99#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
100#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
101#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
Bo Shen3225f342013-05-12 22:40:54 +0000102#endif
103
104#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
Wu, Josha2485582015-01-20 10:33:32 +0800105#define CONFIG_FAT_WRITE
Bo Shen3225f342013-05-12 22:40:54 +0000106#endif
107
108#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
109
110#ifdef CONFIG_SYS_USE_SERIALFLASH
Wu, Josh7a53b952015-08-19 19:11:21 +0800111/* override the bootcmd, bootargs and other configuration for spi flash env*/
Bo Shen3225f342013-05-12 22:40:54 +0000112#elif CONFIG_SYS_USE_NANDFLASH
Wu, Joshdc018fe2015-08-19 19:11:20 +0800113/* override the bootcmd, bootargs and other configuration nandflash env */
Bo Shen3225f342013-05-12 22:40:54 +0000114#elif CONFIG_SYS_USE_MMC
Wu, Josh372ca032015-08-19 19:11:18 +0800115/* override the bootcmd, bootargs and other configuration for sd/mmc env */
Bo Shen3225f342013-05-12 22:40:54 +0000116#else
Bo Shena4c79b32013-08-11 14:26:20 +0000117#define CONFIG_ENV_IS_NOWHERE
Bo Shen3225f342013-05-12 22:40:54 +0000118#endif
119
Bo Shenc5e88852013-11-15 11:12:38 +0800120/* SPL */
Bo Shenc5e88852013-11-15 11:12:38 +0800121#define CONFIG_SPL_FRAMEWORK
122#define CONFIG_SPL_TEXT_BASE 0x300000
Wenyou Yanga97cb062017-04-14 08:51:42 +0800123#define CONFIG_SPL_MAX_SIZE 0x18000
Bo Shenc5e88852013-11-15 11:12:38 +0800124#define CONFIG_SPL_BSS_START_ADDR 0x20000000
125#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
126#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
127#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
128
Bo Shenc5e88852013-11-15 11:12:38 +0800129#define CONFIG_SPL_BOARD_INIT
Bo Shen8a45b0b2014-03-03 14:47:15 +0800130#define CONFIG_SYS_MONITOR_LEN (512 << 10)
131
Bo Shenc5e88852013-11-15 11:12:38 +0800132#ifdef CONFIG_SYS_USE_MMC
Bo Shen993ea972015-03-04 13:32:57 +0800133#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
Paul Kocialkowskie2ccdf82014-11-08 23:14:55 +0100134#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET205b4f32014-10-15 17:53:11 +0200135#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shen8a45b0b2014-03-03 14:47:15 +0800136
Bo Shen27019e42014-03-03 14:47:17 +0800137#elif CONFIG_SYS_USE_NANDFLASH
Bo Shen27019e42014-03-03 14:47:17 +0800138#define CONFIG_SPL_NAND_DRIVERS
139#define CONFIG_SPL_NAND_BASE
140#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
141#define CONFIG_SYS_NAND_5_ADDR_CYCLE
142#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
143#define CONFIG_SYS_NAND_PAGE_COUNT 64
144#define CONFIG_SYS_NAND_OOBSIZE 64
145#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
146#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
Andreas Bießmanne166a832014-05-19 14:23:41 +0200147#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
Bo Shen27019e42014-03-03 14:47:17 +0800148
Bo Shen8a45b0b2014-03-03 14:47:15 +0800149#elif CONFIG_SYS_USE_SERIALFLASH
Bo Shen8a45b0b2014-03-03 14:47:15 +0800150#define CONFIG_SPL_SPI_LOAD
Wenyou Yanga97cb062017-04-14 08:51:42 +0800151#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
Bo Shen8a45b0b2014-03-03 14:47:15 +0800152
Bo Shenc5e88852013-11-15 11:12:38 +0800153#endif
154
Bo Shen3225f342013-05-12 22:40:54 +0000155#endif