blob: 5d4ae68509270288be0c413db7aa08d0ba78e967 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
rickb841b6e2017-05-18 14:37:53 +08002/*
3 * Andestech ATCPIT100 timer driver
4 *
5 * (C) Copyright 2016
6 * Rick Chen, NDS32 Software Engineering, rick@andestech.com
rickb841b6e2017-05-18 14:37:53 +08007 */
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <timer.h>
12#include <linux/io.h>
13
Rick Chen0e920ef2017-11-23 11:04:34 +080014#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2)))
rickb841b6e2017-05-18 14:37:53 +080015
16/*
17 * Definition of register offsets
18 */
19
20/* ID and Revision Register */
21#define ID_REV 0x0
22
23/* Configuration Register */
24#define CFG 0x10
25
26/* Interrupt Enable Register */
27#define INT_EN 0x14
28#define CH_INT_EN(c , i) ((1<<i)<<(4*c))
29
30/* Interrupt Status Register */
31#define INT_STA 0x18
32#define CH_INT_STA(c , i) ((1<<i)<<(4*c))
33
34/* Channel Enable Register */
35#define CH_EN 0x1C
36#define CH_TMR_EN(c , t) ((1<<t)<<(4*c))
37
38/* Ch n Control REgister */
39#define CH_CTL(n) (0x20+0x10*n)
40/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
41#define APB_CLK (1<<3)
42/* Channel mode , bit 0~2 */
43#define TMR_32 1
44#define TMR_16 2
45#define TMR_8 3
46#define PWM 4
47
48#define CH_REL(n) (0x24+0x10*n)
49#define CH_CNT(n) (0x28+0x10*n)
50
51struct atctmr_timer_regs {
52 u32 id_rev; /* 0x00 */
53 u32 reservd[3]; /* 0x04 ~ 0x0c */
54 u32 cfg; /* 0x10 */
55 u32 int_en; /* 0x14 */
56 u32 int_st; /* 0x18 */
57 u32 ch_en; /* 0x1c */
58 u32 ch0_ctrl; /* 0x20 */
59 u32 ch0_reload; /* 0x24 */
60 u32 ch0_cntr; /* 0x28 */
61 u32 reservd1; /* 0x2c */
62 u32 ch1_ctrl; /* 0x30 */
63 u32 ch1_reload; /* 0x34 */
64 u32 int_mask; /* 0x38 */
65};
66
Rick Chen033d4082017-11-23 10:15:20 +080067struct atcpit_timer_platdata {
Rick Chen0e920ef2017-11-23 11:04:34 +080068 u32 *regs;
rickb841b6e2017-05-18 14:37:53 +080069};
70
Rick Chen033d4082017-11-23 10:15:20 +080071static int atcpit_timer_get_count(struct udevice *dev, u64 *count)
rickb841b6e2017-05-18 14:37:53 +080072{
Rick Chenc6c85dc2017-11-28 09:14:20 +080073 struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
rickb841b6e2017-05-18 14:37:53 +080074 u32 val;
75 val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
76 *count = timer_conv_64(val);
77 return 0;
78}
79
Rick Chen033d4082017-11-23 10:15:20 +080080static int atcpit_timer_probe(struct udevice *dev)
rickb841b6e2017-05-18 14:37:53 +080081{
Rick Chenc6c85dc2017-11-28 09:14:20 +080082 struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
rickb841b6e2017-05-18 14:37:53 +080083 REG32_TMR(CH_REL(1)) = 0xffffffff;
84 REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
85 REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
86 return 0;
87}
88
Rick Chen033d4082017-11-23 10:15:20 +080089static int atcpit_timer_ofdata_to_platdata(struct udevice *dev)
rickb841b6e2017-05-18 14:37:53 +080090{
Rick Chen033d4082017-11-23 10:15:20 +080091 struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
Masahiro Yamada25484932020-07-17 14:36:48 +090092 plat->regs = map_physmem(dev_read_addr(dev), 0x100 , MAP_NOCACHE);
rickb841b6e2017-05-18 14:37:53 +080093 return 0;
94}
95
Rick Chen033d4082017-11-23 10:15:20 +080096static const struct timer_ops atcpit_timer_ops = {
97 .get_count = atcpit_timer_get_count,
rickb841b6e2017-05-18 14:37:53 +080098};
99
Rick Chen033d4082017-11-23 10:15:20 +0800100static const struct udevice_id atcpit_timer_ids[] = {
rickb841b6e2017-05-18 14:37:53 +0800101 { .compatible = "andestech,atcpit100" },
102 {}
103};
104
Rick Chen033d4082017-11-23 10:15:20 +0800105U_BOOT_DRIVER(atcpit100_timer) = {
106 .name = "atcpit100_timer",
rickb841b6e2017-05-18 14:37:53 +0800107 .id = UCLASS_TIMER,
Rick Chen033d4082017-11-23 10:15:20 +0800108 .of_match = atcpit_timer_ids,
109 .ofdata_to_platdata = atcpit_timer_ofdata_to_platdata,
110 .platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata),
111 .probe = atcpit_timer_probe,
112 .ops = &atcpit_timer_ops,
rickb841b6e2017-05-18 14:37:53 +0800113};