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Dirk Eibach2da0fc02011-01-21 09:31:21 +01001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __GDSYS_FPGA_H
25#define __GDSYS_FPGA_H
26
Dirk Eibach255ef4d2011-10-20 11:12:55 +020027int init_func_fpga(void);
28
Dirk Eibach2da0fc02011-01-21 09:31:21 +010029enum {
30 FPGA_STATE_DONE_FAILED = 1 << 0,
31 FPGA_STATE_REFLECTION_FAILED = 1 << 1,
Dirk Eibach255ef4d2011-10-20 11:12:55 +020032 FPGA_STATE_PLATFORM = 1 << 2,
Dirk Eibach2da0fc02011-01-21 09:31:21 +010033};
34
35int get_fpga_state(unsigned dev);
36void print_fpga_state(unsigned dev);
37
Dirk Eibach0e60aa82012-04-27 10:33:46 +020038struct ihs_gpio {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010039 u16 read;
40 u16 clear;
41 u16 set;
Dirk Eibach0e60aa82012-04-27 10:33:46 +020042};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010043
Dirk Eibach0e60aa82012-04-27 10:33:46 +020044struct ihs_i2c {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010045 u16 write_mailbox;
46 u16 write_mailbox_ext;
47 u16 read_mailbox;
48 u16 read_mailbox_ext;
Dirk Eibach0e60aa82012-04-27 10:33:46 +020049};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010050
Dirk Eibach0e60aa82012-04-27 10:33:46 +020051struct ihs_osd {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010052 u16 version;
53 u16 features;
54 u16 control;
55 u16 xy_size;
Dirk Eibach52158e32011-04-06 13:53:47 +020056 u16 xy_scale;
57 u16 x_pos;
58 u16 y_pos;
Dirk Eibach0e60aa82012-04-27 10:33:46 +020059};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010060
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000061#ifdef CONFIG_NEO
Dirk Eibach0e60aa82012-04-27 10:33:46 +020062struct ihs_fpga {
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000063 u16 reflection_low; /* 0x0000 */
64 u16 versions; /* 0x0002 */
65 u16 fpga_features; /* 0x0004 */
66 u16 fpga_version; /* 0x0006 */
67 u16 reserved_0[8187]; /* 0x0008 */
68 u16 reflection_high; /* 0x3ffe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +020069};
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000070#endif
71
Dirk Eibach2da0fc02011-01-21 09:31:21 +010072#ifdef CONFIG_IO
Dirk Eibach0e60aa82012-04-27 10:33:46 +020073struct ihs_fpga {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010074 u16 reflection_low; /* 0x0000 */
75 u16 versions; /* 0x0002 */
76 u16 fpga_features; /* 0x0004 */
77 u16 fpga_version; /* 0x0006 */
78 u16 reserved_0[5]; /* 0x0008 */
79 u16 quad_serdes_reset; /* 0x0012 */
80 u16 reserved_1[8181]; /* 0x0014 */
81 u16 reflection_high; /* 0x3ffe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +020082};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010083#endif
84
Dirk Eibach255ef4d2011-10-20 11:12:55 +020085#ifdef CONFIG_IO64
Dirk Eibach0e60aa82012-04-27 10:33:46 +020086struct ihs_fpga {
Dirk Eibach255ef4d2011-10-20 11:12:55 +020087 u16 reflection_low; /* 0x0000 */
88 u16 versions; /* 0x0002 */
89 u16 fpga_features; /* 0x0004 */
90 u16 fpga_version; /* 0x0006 */
91 u16 reserved_0[5]; /* 0x0008 */
92 u16 quad_serdes_reset; /* 0x0012 */
93 u16 reserved_1[502]; /* 0x0014 */
94 u16 ch0_status_int; /* 0x0400 */
95 u16 ch0_config_int; /* 0x0402 */
Dirk Eibach06b17412012-01-02 11:02:46 +010096 u16 reserved_2[126]; /* 0x0404 */
97 u16 ch0_hicb_status_int;/* 0x0500 */
98 u16 ch0_hicb_config_int;/* 0x0502 */
99 u16 reserved_3[7549]; /* 0x0504 */
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200100 u16 reflection_high; /* 0x3ffe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200101};
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200102#endif
103
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100104#ifdef CONFIG_IOCON
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200105struct ihs_fpga {
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100106 u16 reflection_low; /* 0x0000 */
107 u16 versions; /* 0x0002 */
108 u16 fpga_version; /* 0x0004 */
109 u16 fpga_features; /* 0x0006 */
110 u16 reserved_0[6]; /* 0x0008 */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200111 struct ihs_gpio gpio; /* 0x0014 */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100112 u16 mpc3w_control; /* 0x001a */
113 u16 reserved_1[19]; /* 0x001c */
114 u16 videocontrol; /* 0x0042 */
115 u16 reserved_2[93]; /* 0x0044 */
116 u16 reflection_high; /* 0x00fe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200117 struct ihs_osd osd; /* 0x0100 */
Dirk Eibach530846b2012-04-26 03:54:26 +0000118 u16 reserved_3[889]; /* 0x010e */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100119 u16 videomem; /* 0x0800 */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200120};
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100121#endif
122
123#ifdef CONFIG_DLVISION_10G
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200124struct ihs_fpga {
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100125 u16 reflection_low; /* 0x0000 */
126 u16 versions; /* 0x0002 */
127 u16 fpga_version; /* 0x0004 */
128 u16 fpga_features; /* 0x0006 */
129 u16 reserved_0[10]; /* 0x0008 */
130 u16 extended_interrupt; /* 0x001c */
131 u16 reserved_1[9]; /* 0x001e */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200132 struct ihs_i2c i2c; /* 0x0030 */
Dirk Eibach7749c842011-04-06 13:53:48 +0200133 u16 reserved_2[16]; /* 0x0038 */
134 u16 mpc3w_control; /* 0x0058 */
135 u16 reserved_3[34]; /* 0x005a */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100136 u16 videocontrol; /* 0x009e */
Dirk Eibach7749c842011-04-06 13:53:48 +0200137 u16 reserved_4[176]; /* 0x00a0 */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200138 struct ihs_osd osd; /* 0x0200 */
Dirk Eibach7749c842011-04-06 13:53:48 +0200139 u16 reserved_5[761]; /* 0x020e */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100140 u16 videomem; /* 0x0800 */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200141};
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100142#endif
143
144#endif