blob: 510838d2f5250bbf7a27d1917602501a7e806674 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek4e779ad2013-04-24 10:01:20 +02002/*
Michal Simek10441ec2018-07-12 16:05:46 +02003 * Copyright (c) 2013 - 2018 Xilinx, Michal Simek
Michal Simek4e779ad2013-04-24 10:01:20 +02004 */
5
6#include <common.h>
7#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06008#include <log.h>
Michal Simek4e779ad2013-04-24 10:01:20 +02009#include <malloc.h>
10#include <linux/list.h>
11#include <asm/io.h>
12#include <asm/gpio.h>
Michal Simek10441ec2018-07-12 16:05:46 +020013#include <dm.h>
Michal Simek6f81ff02018-07-23 13:40:01 +020014#include <dt-bindings/gpio/gpio.h>
Michal Simek4e779ad2013-04-24 10:01:20 +020015
Michal Simek6f81ff02018-07-23 13:40:01 +020016#define XILINX_GPIO_MAX_BANK 2
Michal Simek4e779ad2013-04-24 10:01:20 +020017
18/* Gpio simple map */
19struct gpio_regs {
20 u32 gpiodata;
21 u32 gpiodir;
22};
23
Simon Glass8a8d24b2020-12-03 16:55:23 -070024struct xilinx_gpio_plat {
Michal Simek10441ec2018-07-12 16:05:46 +020025 struct gpio_regs *regs;
26 int bank_max[XILINX_GPIO_MAX_BANK];
27 int bank_input[XILINX_GPIO_MAX_BANK];
28 int bank_output[XILINX_GPIO_MAX_BANK];
Michal Simekc714aea2018-07-23 12:40:36 +020029 u32 dout_default[XILINX_GPIO_MAX_BANK];
30};
31
32struct xilinx_gpio_privdata {
33 u32 output_val[XILINX_GPIO_MAX_BANK];
Michal Simek10441ec2018-07-12 16:05:46 +020034};
35
36static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
37 u32 *bank_pin_num, struct udevice *dev)
38{
Simon Glass8a8d24b2020-12-03 16:55:23 -070039 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
Michal Simek10441ec2018-07-12 16:05:46 +020040 u32 bank, max_pins;
41 /* the first gpio is 0 not 1 */
42 u32 pin_num = offset;
43
44 for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
Simon Glasscaa4daa2020-12-03 16:55:18 -070045 max_pins = plat->bank_max[bank];
Michal Simek10441ec2018-07-12 16:05:46 +020046 if (pin_num < max_pins) {
47 debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
48 bank, pin_num);
49 *bank_num = bank;
50 *bank_pin_num = pin_num;
51 return 0;
52 }
53 pin_num -= max_pins;
54 }
55
56 return -EINVAL;
57}
58
59static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
60 int value)
61{
Simon Glass8a8d24b2020-12-03 16:55:23 -070062 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
Michal Simekc714aea2018-07-23 12:40:36 +020063 struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
Michal Simek10441ec2018-07-12 16:05:46 +020064 int val, ret;
65 u32 bank, pin;
66
67 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
68 if (ret)
69 return ret;
70
Michal Simekc714aea2018-07-23 12:40:36 +020071 val = priv->output_val[bank];
Michal Simek642a8602018-07-30 14:29:27 +020072
Michal Simekc714aea2018-07-23 12:40:36 +020073 debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
Simon Glasscaa4daa2020-12-03 16:55:18 -070074 __func__, (ulong)plat->regs, value, offset, bank, pin, val);
Michal Simek10441ec2018-07-12 16:05:46 +020075
Michal Simek642a8602018-07-30 14:29:27 +020076 if (value)
Michal Simek10441ec2018-07-12 16:05:46 +020077 val = val | (1 << pin);
Michal Simek642a8602018-07-30 14:29:27 +020078 else
Michal Simek10441ec2018-07-12 16:05:46 +020079 val = val & ~(1 << pin);
Michal Simek642a8602018-07-30 14:29:27 +020080
Simon Glasscaa4daa2020-12-03 16:55:18 -070081 writel(val, &plat->regs->gpiodata + bank * 2);
Michal Simek10441ec2018-07-12 16:05:46 +020082
Michal Simekc714aea2018-07-23 12:40:36 +020083 priv->output_val[bank] = val;
84
Michal Simekac7f0612018-08-06 07:42:40 +020085 return 0;
Michal Simek10441ec2018-07-12 16:05:46 +020086};
87
88static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
89{
Simon Glass8a8d24b2020-12-03 16:55:23 -070090 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
Michal Simekc714aea2018-07-23 12:40:36 +020091 struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
Michal Simek10441ec2018-07-12 16:05:46 +020092 int val, ret;
93 u32 bank, pin;
94
95 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
96 if (ret)
97 return ret;
98
99 debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
Simon Glasscaa4daa2020-12-03 16:55:18 -0700100 (ulong)plat->regs, offset, bank, pin);
Michal Simek10441ec2018-07-12 16:05:46 +0200101
Simon Glasscaa4daa2020-12-03 16:55:18 -0700102 if (plat->bank_output[bank]) {
Michal Simekc714aea2018-07-23 12:40:36 +0200103 debug("%s: Read saved output value\n", __func__);
104 val = priv->output_val[bank];
105 } else {
106 debug("%s: Read input value from reg\n", __func__);
Simon Glasscaa4daa2020-12-03 16:55:18 -0700107 val = readl(&plat->regs->gpiodata + bank * 2);
Michal Simekc714aea2018-07-23 12:40:36 +0200108 }
109
Michal Simek10441ec2018-07-12 16:05:46 +0200110 val = !!(val & (1 << pin));
111
112 return val;
113};
114
115static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
116{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700117 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
Michal Simek10441ec2018-07-12 16:05:46 +0200118 int val, ret;
119 u32 bank, pin;
120
Michal Simekddd7b3f2018-07-23 12:08:49 +0200121 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
122 if (ret)
123 return ret;
124
Michal Simek10441ec2018-07-12 16:05:46 +0200125 /* Check if all pins are inputs */
Simon Glasscaa4daa2020-12-03 16:55:18 -0700126 if (plat->bank_input[bank])
Michal Simek10441ec2018-07-12 16:05:46 +0200127 return GPIOF_INPUT;
128
129 /* Check if all pins are outputs */
Simon Glasscaa4daa2020-12-03 16:55:18 -0700130 if (plat->bank_output[bank])
Michal Simek10441ec2018-07-12 16:05:46 +0200131 return GPIOF_OUTPUT;
132
Michal Simek10441ec2018-07-12 16:05:46 +0200133 /* FIXME test on dual */
Simon Glasscaa4daa2020-12-03 16:55:18 -0700134 val = readl(&plat->regs->gpiodir + bank * 2);
Michal Simek10441ec2018-07-12 16:05:46 +0200135 val = !(val & (1 << pin));
136
137 /* input is 1 in reg but GPIOF_INPUT is 0 */
138 /* output is 0 in reg but GPIOF_OUTPUT is 1 */
139
140 return val;
141}
142
143static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
144 int value)
145{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700146 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
Michal Simek10441ec2018-07-12 16:05:46 +0200147 int val, ret;
148 u32 bank, pin;
149
150 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
151 if (ret)
152 return ret;
153
154 /* can't change it if all is input by default */
Simon Glasscaa4daa2020-12-03 16:55:18 -0700155 if (plat->bank_input[bank])
Michal Simek10441ec2018-07-12 16:05:46 +0200156 return -EINVAL;
157
Michal Simekbf2a69d2018-07-30 10:02:53 +0200158 xilinx_gpio_set_value(dev, offset, value);
159
Simon Glasscaa4daa2020-12-03 16:55:18 -0700160 if (!plat->bank_output[bank]) {
161 val = readl(&plat->regs->gpiodir + bank * 2);
Michal Simek10441ec2018-07-12 16:05:46 +0200162 val = val & ~(1 << pin);
Simon Glasscaa4daa2020-12-03 16:55:18 -0700163 writel(val, &plat->regs->gpiodir + bank * 2);
Michal Simek10441ec2018-07-12 16:05:46 +0200164 }
165
Michal Simek10441ec2018-07-12 16:05:46 +0200166 return 0;
167}
168
169static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
170{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700171 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
Michal Simek10441ec2018-07-12 16:05:46 +0200172 int val, ret;
173 u32 bank, pin;
174
175 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
176 if (ret)
177 return ret;
178
179 /* Already input */
Simon Glasscaa4daa2020-12-03 16:55:18 -0700180 if (plat->bank_input[bank])
Michal Simek10441ec2018-07-12 16:05:46 +0200181 return 0;
182
183 /* can't change it if all is output by default */
Simon Glasscaa4daa2020-12-03 16:55:18 -0700184 if (plat->bank_output[bank])
Michal Simek10441ec2018-07-12 16:05:46 +0200185 return -EINVAL;
186
Simon Glasscaa4daa2020-12-03 16:55:18 -0700187 val = readl(&plat->regs->gpiodir + bank * 2);
Michal Simek10441ec2018-07-12 16:05:46 +0200188 val = val | (1 << pin);
Simon Glasscaa4daa2020-12-03 16:55:18 -0700189 writel(val, &plat->regs->gpiodir + bank * 2);
Michal Simek10441ec2018-07-12 16:05:46 +0200190
191 return 0;
192}
193
194static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
195 struct ofnode_phandle_args *args)
196{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700197 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
Michal Simek10441ec2018-07-12 16:05:46 +0200198
199 desc->offset = args->args[0];
200
201 debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
202 args->args_count, args->args[0], args->args[1], args->args[2]);
203
204 /*
205 * The second cell is channel offset:
206 * 0 is first channel, 8 is second channel
207 *
208 * U-Boot driver just combine channels together that's why simply
209 * add amount of pins in second channel if present.
210 */
211 if (args->args[1]) {
Simon Glasscaa4daa2020-12-03 16:55:18 -0700212 if (!plat->bank_max[1]) {
Michal Simek10441ec2018-07-12 16:05:46 +0200213 printf("%s: %s has no second channel\n",
214 __func__, dev->name);
215 return -EINVAL;
216 }
217
Simon Glasscaa4daa2020-12-03 16:55:18 -0700218 desc->offset += plat->bank_max[0];
Michal Simek10441ec2018-07-12 16:05:46 +0200219 }
220
221 /* The third cell is optional */
222 if (args->args_count > 2)
223 desc->flags = (args->args[2] &
224 GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
225
226 debug("%s: offset %x, flags %lx\n",
227 __func__, desc->offset, desc->flags);
228 return 0;
229}
230
231static const struct dm_gpio_ops xilinx_gpio_ops = {
232 .direction_input = xilinx_gpio_direction_input,
233 .direction_output = xilinx_gpio_direction_output,
234 .get_value = xilinx_gpio_get_value,
235 .set_value = xilinx_gpio_set_value,
236 .get_function = xilinx_gpio_get_function,
237 .xlate = xilinx_gpio_xlate,
238};
239
240static int xilinx_gpio_probe(struct udevice *dev)
241{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700242 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
Michal Simekc714aea2018-07-23 12:40:36 +0200243 struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
Michal Simek10441ec2018-07-12 16:05:46 +0200244 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Michal Simek312dd1c2018-08-02 12:58:54 +0200245 const void *label_ptr;
Michal Simek10441ec2018-07-12 16:05:46 +0200246
Michal Simek312dd1c2018-08-02 12:58:54 +0200247 label_ptr = dev_read_prop(dev, "label", NULL);
248 if (label_ptr) {
249 uc_priv->bank_name = strdup(label_ptr);
250 if (!uc_priv->bank_name)
251 return -ENOMEM;
252 } else {
253 uc_priv->bank_name = dev->name;
254 }
Michal Simek10441ec2018-07-12 16:05:46 +0200255
Simon Glasscaa4daa2020-12-03 16:55:18 -0700256 uc_priv->gpio_count = plat->bank_max[0] + plat->bank_max[1];
Michal Simek10441ec2018-07-12 16:05:46 +0200257
Simon Glasscaa4daa2020-12-03 16:55:18 -0700258 priv->output_val[0] = plat->dout_default[0];
Michal Simekc714aea2018-07-23 12:40:36 +0200259
Simon Glasscaa4daa2020-12-03 16:55:18 -0700260 if (plat->bank_max[1])
261 priv->output_val[1] = plat->dout_default[1];
Michal Simekc714aea2018-07-23 12:40:36 +0200262
Michal Simek10441ec2018-07-12 16:05:46 +0200263 return 0;
264}
265
Simon Glassd1998a92020-12-03 16:55:21 -0700266static int xilinx_gpio_of_to_plat(struct udevice *dev)
Michal Simek10441ec2018-07-12 16:05:46 +0200267{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700268 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
Michal Simek10441ec2018-07-12 16:05:46 +0200269 int is_dual;
270
Simon Glasscaa4daa2020-12-03 16:55:18 -0700271 plat->regs = (struct gpio_regs *)dev_read_addr(dev);
Michal Simek10441ec2018-07-12 16:05:46 +0200272
Simon Glasscaa4daa2020-12-03 16:55:18 -0700273 plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0);
274 plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0);
275 plat->bank_output[0] = dev_read_u32_default(dev, "xlnx,all-outputs", 0);
276 plat->dout_default[0] = dev_read_u32_default(dev, "xlnx,dout-default",
277 0);
Michal Simek10441ec2018-07-12 16:05:46 +0200278
279 is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
280 if (is_dual) {
Simon Glasscaa4daa2020-12-03 16:55:18 -0700281 plat->bank_max[1] = dev_read_u32_default(dev,
282 "xlnx,gpio2-width", 0);
283 plat->bank_input[1] = dev_read_u32_default(dev,
Michal Simek10441ec2018-07-12 16:05:46 +0200284 "xlnx,all-inputs-2", 0);
Simon Glasscaa4daa2020-12-03 16:55:18 -0700285 plat->bank_output[1] = dev_read_u32_default(dev,
Michal Simek10441ec2018-07-12 16:05:46 +0200286 "xlnx,all-outputs-2", 0);
Simon Glasscaa4daa2020-12-03 16:55:18 -0700287 plat->dout_default[1] = dev_read_u32_default(dev,
Michal Simekc714aea2018-07-23 12:40:36 +0200288 "xlnx,dout-default-2", 0);
Michal Simek10441ec2018-07-12 16:05:46 +0200289 }
290
291 return 0;
292}
293
294static const struct udevice_id xilinx_gpio_ids[] = {
295 { .compatible = "xlnx,xps-gpio-1.00.a",},
296 { }
297};
298
299U_BOOT_DRIVER(xilinx_gpio) = {
300 .name = "xlnx_gpio",
301 .id = UCLASS_GPIO,
302 .ops = &xilinx_gpio_ops,
303 .of_match = xilinx_gpio_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700304 .of_to_plat = xilinx_gpio_of_to_plat,
Michal Simek10441ec2018-07-12 16:05:46 +0200305 .probe = xilinx_gpio_probe,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700306 .plat_auto = sizeof(struct xilinx_gpio_plat),
Simon Glass41575d82020-12-03 16:55:17 -0700307 .priv_auto = sizeof(struct xilinx_gpio_privdata),
Michal Simek10441ec2018-07-12 16:05:46 +0200308};