blob: 99e4e9051fc6adafd2ea2659bd9766256499213b [file] [log] [blame]
Andre Schwarz5e0de0e2008-07-09 18:30:44 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2008
6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Andre Schwarz5e0de0e2008-07-09 18:30:44 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#include <version.h>
15
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020016#define CONFIG_MPC5200 1
17
Wolfgang Denk2ae18242010-10-06 09:05:45 +020018#ifndef CONFIG_SYS_TEXT_BASE
19#define CONFIG_SYS_TEXT_BASE 0xFF800000
20#endif
21
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020023
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020024#define CONFIG_MISC_INIT_R 1
25
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denk17e900b2008-08-12 14:54:04 +020027#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#define CONFIG_SYS_CACHELINE_SHIFT 5
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020029#endif
30
31#define CONFIG_PSC_CONSOLE 1
32#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020034
35#define CONFIG_PCI 1
36#define CONFIG_PCI_PNP 1
37#undef CONFIG_PCI_SCAN_SHOW
38#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
39
40#define CONFIG_PCI_MEM_BUS 0x40000000
41#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
42#define CONFIG_PCI_MEM_SIZE 0x10000000
43
44#define CONFIG_PCI_IO_BUS 0x50000000
45#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
46#define CONFIG_PCI_IO_SIZE 0x01000000
47
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_XLB_PIPELINING 1
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020049#define CONFIG_HIGH_BATS 1
50
51#define MV_CI mvBlueCOUGAR-P
52#define MV_VCI mvBlueCOUGAR-P
53#define MV_FPGA_DATA 0xff860000
André Schwarz28887d82009-08-27 14:48:35 +020054#define MV_FPGA_SIZE 0
André Schwarze3b39f82009-07-17 14:50:24 +020055#define MV_KERNEL_ADDR 0xffd00000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020056#define MV_INITRD_ADDR 0xff900000
André Schwarze3b39f82009-07-17 14:50:24 +020057#define MV_INITRD_LENGTH 0x00400000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020058#define MV_SCRATCH_ADDR 0x00000000
59#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
Peter Tyser3202d332009-09-16 21:38:10 -050060#define MV_SCRIPT_ADDR 0xff840000
61#define MV_SCRIPT_ADDR2 0xff850000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020062#define MV_DTB_ADDR 0xfffc0000
63
64#define CONFIG_SHOW_BOOT_PROGRESS 1
65
66#define MV_KERNEL_ADDR_RAM 0x00100000
67#define MV_DTB_ADDR_RAM 0x00600000
68#define MV_INITRD_ADDR_RAM 0x01000000
69
70/* pass open firmware flat tree */
71#define CONFIG_OF_LIBFDT 1
72#define CONFIG_OF_BOARD_SETUP 1
73
74#define OF_CPU "PowerPC,5200@0"
75#define OF_SOC "soc5200@f0000000"
76#define OF_TBCLK (bd->bi_busfreq / 4)
77#define MV_DTB_NAME mvbc-p.dtb
78#define CONFIG_OF_STDOUT_VIA_ALIAS 1
79
80/*
81 * Supported commands
82 */
83#include <config_cmd_default.h>
84
85#define CONFIG_CMD_CACHE
86#define CONFIG_CMD_NET
87#define CONFIG_CMD_PING
88#define CONFIG_CMD_DHCP
89#define CONFIG_CMD_SDRAM
90#define CONFIG_CMD_PCI
91#define CONFIG_CMD_FPGA
André Schwarze3b39f82009-07-17 14:50:24 +020092#define CONFIG_CMD_I2C
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020093
94#undef CONFIG_WATCHDOG
95
96#define CONFIG_BOOTP_VENDOREX
97#define CONFIG_BOOTP_SUBNETMASK
98#define CONFIG_BOOTP_GATEWAY
99#define CONFIG_BOOTP_DNS
100#define CONFIG_BOOTP_DNS2
101#define CONFIG_BOOTP_HOSTNAME
102#define CONFIG_BOOTP_BOOTFILESIZE
103#define CONFIG_BOOTP_BOOTPATH
104#define CONFIG_BOOTP_NTPSERVER
105#define CONFIG_BOOTP_RANDOM_DELAY
106#define CONFIG_BOOTP_SEND_HOSTNAME
107
108/*
109 * Autoboot
110 */
111#define CONFIG_BOOTDELAY 2
112#define CONFIG_AUTOBOOT_KEYED
113#define CONFIG_AUTOBOOT_STOP_STR "s"
114#define CONFIG_ZERO_BOOTDELAY_CHECK
115#define CONFIG_RESET_TO_RETRY 1000
116
Peter Tyser3202d332009-09-16 21:38:10 -0500117#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
118 then source ${script_addr}; \
119 else source ${script_addr2}; \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200120 fi;"
121
122#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
123#define CONFIG_ENV_OVERWRITE
124
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200125#define CONFIG_EXTRA_ENV_SETTINGS \
126 "console_nr=0\0" \
127 "console=yes\0" \
128 "stdin=serial\0" \
129 "stdout=serial\0" \
130 "stderr=serial\0" \
131 "fpga=0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200132 "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
133 "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
134 "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
135 "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
136 "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
137 "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
138 "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
139 "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
140 "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
141 "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
142 "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
143 "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
144 "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
145 "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200146 "mv_version=" U_BOOT_VERSION "\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200147 "dhcp_client_id=" __stringify(MV_CI) "\0" \
148 "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200149 "netretry=no\0" \
150 "use_static_ipaddr=no\0" \
151 "static_ipaddr=192.168.90.10\0" \
152 "static_netmask=255.255.255.0\0" \
153 "static_gateway=0.0.0.0\0" \
154 "initrd_name=uInitrd.mvbc-p-rfs\0" \
155 "zcip=no\0" \
156 "netboot=yes\0" \
157 "mvtest=Ff\0" \
158 "tried_bootfromflash=no\0" \
159 "tried_bootfromnet=no\0" \
160 "use_dhcp=yes\0" \
161 "gev_start=yes\0" \
162 "mvbcdma_debug=0\0" \
163 "mvbcia_debug=0\0" \
164 "propdev_debug=0\0" \
165 "gevss_debug=0\0" \
166 "watchdog=1\0" \
André Schwarze3b39f82009-07-17 14:50:24 +0200167 "sensor_cnt=1\0" \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200168 ""
169
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200170/*
171 * IPB Bus clocking configuration.
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
174#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200175
176/*
177 * Flash configuration
178 */
179#undef CONFIG_FLASH_16BIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200181#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
183#define CONFIG_SYS_FLASH_EMPTY_INFO
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
186#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MAX_FLASH_BANKS 1
189#define CONFIG_SYS_MAX_FLASH_SECT 256
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_LOWBOOT
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200192#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_SIZE 0x00800000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200194
195/*
196 * Environment settings
197 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200198#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#undef CONFIG_SYS_FLASH_PROTECTION
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200200
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200201#define CONFIG_ENV_ADDR 0xFFFE0000
202#define CONFIG_ENV_SIZE 0x10000
203#define CONFIG_ENV_SECT_SIZE 0x10000
204#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
205#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200206
207/*
208 * Memory map
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MBAR 0xF0000000
211#define CONFIG_SYS_SDRAM_BASE 0x00000000
212#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200215#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200216
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200217#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200219
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200220#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
222#define CONFIG_SYS_RAMBOOT 1
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200223#endif
224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
226#define CONFIG_SYS_MONITOR_LEN (512 << 10)
227#define CONFIG_SYS_MALLOC_LEN (512 << 10)
228#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200229
230/*
André Schwarze3b39f82009-07-17 14:50:24 +0200231 * I2C configuration
232 */
233#define CONFIG_HARD_I2C 1
234#define CONFIG_SYS_I2C_MODULE 1
235#define CONFIG_SYS_I2C_SPEED 86000
236#define CONFIG_SYS_I2C_SLAVE 0x7F
237
238/*
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200239 * Ethernet configuration
240 */
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200241#define CONFIG_NET_RETRY_COUNT 5
242
243#define CONFIG_E1000
Wolfgang Denkc4ec6db2008-07-31 13:57:20 +0200244#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200245#undef CONFIG_MPC5xxx_FEC
246#undef CONFIG_PHY_ADDR
247#define CONFIG_NETDEV eth0
248
249/*
250 * Miscellaneous configurable options
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_HUSH_PARSER
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200253#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#undef CONFIG_SYS_LONGHELP
Wolfgang Denk17e900b2008-08-12 14:54:04 +0200255#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_CBSIZE 1024
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200257#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_CBSIZE 256
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200259#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
261#define CONFIG_SYS_MAXARGS 16
262#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_MEMTEST_START 0x00800000
265#define CONFIG_SYS_MEMTEST_END 0x02f00000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200266
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200267/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_LOAD_ADDR 0x02000000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200269/* default location for tftp and bootm */
270#define CONFIG_LOADADDR 0x00200000
271
272/*
273 * Various low-level settings
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
278#define CONFIG_SYS_HID0_FINAL HID0_ICE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
281#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
282#define CONFIG_SYS_BOOTCS_CFG 0x00047800
283#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
284#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_CS_BURST 0x000000f0
287#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_RESET_ADDRESS 0x00000100
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200290
291#undef FPGA_DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
Michal Simekb03b25c2013-05-01 18:05:56 +0200293#define CONFIG_FPGA
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200294#define CONFIG_FPGA_ALTERA 1
295#define CONFIG_FPGA_CYCLON2 1
296#define CONFIG_FPGA_COUNT 1
297
298#endif