blob: c36cf33f070cdfff7fc7e6e4aa29fd0584704bf7 [file] [log] [blame]
Wolfgang Denk52568c32009-05-16 10:47:46 +02001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009, DAVE Srl <www.dave.eu>
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk52568c32009-05-16 10:47:46 +02006 */
7
8/*
9 * Aria board configuration file
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_ARIA 1
16/*
17 * Memory map for the ARIA board:
18 *
19 * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
20 * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
21 * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6
22 * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2
23 * 0x8000_0000-0x803F_FFFF IMMR (4 MB)
24 * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB)
25 * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB)
26 * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
27 * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
28 */
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_E300 1 /* E300 Family */
Wolfgang Denk52568c32009-05-16 10:47:46 +020034#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
Wolfgang Denk52568c32009-05-16 10:47:46 +020035
Wolfgang Denk2ae18242010-10-06 09:05:45 +020036#define CONFIG_SYS_TEXT_BASE 0xFFF00000
37
Wolfgang Denk52568c32009-05-16 10:47:46 +020038/* video */
39#undef CONFIG_VIDEO
40
41#if defined(CONFIG_VIDEO)
42#define CONFIG_CFB_CONSOLE
43#define CONFIG_VGA_AS_SINGLE_DEVICE
44#endif
45
46/* CONFIG_PCI is defined at config time */
47
48#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */
49
Wolfgang Denk52568c32009-05-16 10:47:46 +020050#define CONFIG_MISC_INIT_R
51
52#define CONFIG_SYS_IMMR 0x80000000
53#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
54
55#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
56#define CONFIG_SYS_MEMTEST_END 0x00400000
57
58/*
59 * DDR Setup - manually set all parameters as there's no SPD etc.
60 */
61#define CONFIG_SYS_DDR_SIZE 256 /* MB */
62#define CONFIG_SYS_DDR_BASE 0x00000000
63#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Anatolij Gustschinb9947bb2010-04-24 19:27:08 +020064#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
Wolfgang Denk52568c32009-05-16 10:47:46 +020065
Anatolij Gustschin5d937e82010-04-24 19:27:07 +020066#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
67
Wolfgang Denk52568c32009-05-16 10:47:46 +020068/* DDR Controller Configuration
69 *
70 * SYS_CFG:
71 * [31:31] MDDRC Soft Reset: Diabled
72 * [30:30] DRAM CKE pin: Enabled
73 * [29:29] DRAM CLK: Enabled
74 * [28:28] Command Mode: Enabled (For initialization only)
75 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
76 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
77 * [20:19] Read Test: DON'T USE
78 * [18:18] Self Refresh: Enabled
79 * [17:17] 16bit Mode: Disabled
80 * [16:13] Ready Delay: 2
81 * [12:12] Half DQS Delay: Disabled
82 * [11:11] Quarter DQS Delay: Disabled
83 * [10:08] Write Delay: 2
84 * [07:07] Early ODT: Disabled
85 * [06:06] On DIE Termination: Disabled
86 * [05:05] FIFO Overflow Clear: DON'T USE here
87 * [04:04] FIFO Underflow Clear: DON'T USE here
88 * [03:03] FIFO Overflow Pending: DON'T USE here
89 * [02:02] FIFO Underlfow Pending: DON'T USE here
90 * [01:01] FIFO Overlfow Enabled: Enabled
91 * [00:00] FIFO Underflow Enabled: Enabled
92 * TIME_CFG0
93 * [31:16] DRAM Refresh Time: 0 CSB clocks
94 * [15:8] DRAM Command Time: 0 CSB clocks
95 * [07:00] DRAM Precharge Time: 0 CSB clocks
96 * TIME_CFG1
97 * [31:26] DRAM tRFC:
98 * [25:21] DRAM tWR1:
99 * [20:17] DRAM tWRT1:
100 * [16:11] DRAM tDRR:
101 * [10:05] DRAM tRC:
102 * [04:00] DRAM tRAS:
103 * TIME_CFG2
104 * [31:28] DRAM tRCD:
105 * [27:23] DRAM tFAW:
106 * [22:19] DRAM tRTW1:
107 * [18:15] DRAM tCCD:
108 * [14:10] DRAM tRTP:
109 * [09:05] DRAM tRP:
110 * [04:00] DRAM tRPA
111 */
Wolfgang Denk25671c82009-06-14 20:58:48 +0200112#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \
113 (1 << 30) | /* CKE */ \
114 (1 << 29) | /* CLK_ON */ \
Martha M Stan054197b2009-09-21 14:07:14 -0400115 (0 << 28) | /* CMD_MODE */ \
Wolfgang Denk25671c82009-06-14 20:58:48 +0200116 (4 << 25) | /* DRAM_ROW_SELECT */ \
117 (3 << 21) | /* DRAM_BANK_SELECT */ \
118 (0 << 18) | /* SELF_REF_EN */ \
119 (0 << 17) | /* 16BIT_MODE */ \
120 (2 << 13) | /* RDLY */ \
121 (0 << 12) | /* HALF_DQS_DLY */ \
122 (1 << 11) | /* QUART_DQS_DLY */ \
123 (2 << 8) | /* WDLY */ \
124 (0 << 7) | /* EARLY_ODT */ \
125 (1 << 6) | /* ON_DIE_TERMINATE */ \
126 (0 << 5) | /* FIFO_OV_CLEAR */ \
127 (0 << 4) | /* FIFO_UV_CLEAR */ \
128 (0 << 1) | /* FIFO_OV_EN */ \
129 (0 << 0) /* FIFO_UV_EN */ \
130 )
131
Martha M Stan054197b2009-09-21 14:07:14 -0400132#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
Wolfgang Denk25671c82009-06-14 20:58:48 +0200133#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
134#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
Wolfgang Denk52568c32009-05-16 10:47:46 +0200135
Martha M Stan054197b2009-09-21 14:07:14 -0400136#define CONFIG_SYS_DDRCMD_NOP 0x01380000
137#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
Wolfgang Denk25671c82009-06-14 20:58:48 +0200138#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \
139 (0 << 22) | /* DRAM_CS */ \
140 (0 << 21) | /* DRAM_RAS */ \
141 (0 << 20) | /* DRAM_CAS */ \
142 (0 << 19) | /* DRAM_WEB */ \
143 (1 << 16) | /* DRAM_BS[2:0] */ \
144 (0 << 15) | /* */ \
145 (0 << 12) | /* A12->out */ \
146 (0 << 11) | /* A11->RDQS */ \
147 (0 << 10) | /* A10->DQS# */ \
148 (0 << 7) | /* OCD program */ \
149 (0 << 6) | /* Rtt1 */ \
150 (0 << 3) | /* posted CAS# */ \
151 (0 << 2) | /* Rtt0 */ \
152 (1 << 1) | /* ODS */ \
153 (0 << 0) /* DLL */ \
154 )
155#define CONFIG_SYS_MICRON_EMR2 0x01020000
156#define CONFIG_SYS_MICRON_EMR3 0x01030000
Martha M Stan054197b2009-09-21 14:07:14 -0400157#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
Wolfgang Denk52568c32009-05-16 10:47:46 +0200158#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
Wolfgang Denk25671c82009-06-14 20:58:48 +0200159#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \
160 (0 << 22) | /* DRAM_CS */ \
161 (0 << 21) | /* DRAM_RAS */ \
162 (0 << 20) | /* DRAM_CAS */ \
163 (0 << 19) | /* DRAM_WEB */ \
164 (1 << 16) | /* DRAM_BS[2:0] */ \
165 (0 << 15) | /* */ \
166 (0 << 12) | /* A12->out */ \
167 (0 << 11) | /* A11->RDQS */ \
168 (1 << 10) | /* A10->DQS# */ \
169 (7 << 7) | /* OCD program */ \
170 (0 << 6) | /* Rtt1 */ \
171 (0 << 3) | /* posted CAS# */ \
172 (1 << 2) | /* Rtt0 */ \
173 (0 << 1) | /* ODS (Output Drive Strength) */ \
174 (0 << 0) /* DLL */ \
175 )
176
177/*
178 * Backward compatible definitions,
Stefan Roesea47a12b2010-04-15 16:07:28 +0200179 * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
Wolfgang Denk25671c82009-06-14 20:58:48 +0200180 */
Martha M Stan054197b2009-09-21 14:07:14 -0400181#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
182#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
183#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
184#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200185
186/* DDR Priority Manager Configuration */
187#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
188#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
189#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
190#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
191#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
192#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
193#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
194#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
195#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
196#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
197#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
198#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
199#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
200#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
201#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
202#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
203#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
204#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
205#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
206#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
207#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
208#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
209#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
210
211/*
212 * NOR FLASH on the Local Bus
213 */
214#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
215#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
216#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */
217#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */
218
219#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
220#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
221#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
222#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */
223
224#undef CONFIG_SYS_FLASH_CHECKSUM
225
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200226/*
227 * NAND FLASH support
228 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
229 */
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200230#define CONFIG_CMD_NAND /* enable NAND support */
231#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200232#define CONFIG_NAND_MPC5121_NFC
233#define CONFIG_SYS_NAND_BASE 0x40000000
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200234#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200235
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200236/*
237 * Configuration parameters for MPC5121 NAND driver
238 */
239#define CONFIG_FSL_NFC_WIDTH 1
240#define CONFIG_FSL_NFC_WRITE_SIZE 2048
241#define CONFIG_FSL_NFC_SPARE_SIZE 64
242#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
243
Wolfgang Denk52568c32009-05-16 10:47:46 +0200244#define CONFIG_SYS_SRAM_BASE 0x30000000
245#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
246
Wolfgang Denk25671c82009-06-14 20:58:48 +0200247/* Make two SRAM regions contiguous */
248#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
249 CONFIG_SYS_SRAM_SIZE)
250#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000251#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE
252#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200253
254#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
255 CONFIG_SYS_ARIA_SRAM_SIZE)
256#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */
257
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000258#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE
259#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE
260
Wolfgang Denk52568c32009-05-16 10:47:46 +0200261#define CONFIG_SYS_CS0_CFG 0x05059150
262#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
263 (5 << 16) | \
264 (1 << 15) | \
265 (0 << 14) | \
266 (0 << 13) | \
267 (1 << 12) | \
268 (0 << 10) | \
269 (3 << 8) | /* 32 bit */ \
270 (0 << 7) | \
271 (1 << 6) | \
272 (1 << 4) | \
273 (0 << 3) | \
274 (0 << 2) | \
275 (0 << 1) | \
276 (0 << 0) \
277 )
278#define CONFIG_SYS_CS6_CFG 0x05059150
279
280/* Use alternative CS timing for CS0 and CS2 */
281#define CONFIG_SYS_CS_ALETIMING 0x00000005
282
283/* Use SRAM for initial stack */
284#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
Wolfgang Denk553f0982010-10-26 13:32:32 +0200285#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200286
Wolfgang Denk553f0982010-10-26 13:32:32 +0200287#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200288 GENERATED_GBL_DATA_SIZE)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200289#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
290
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200291#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200292#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200293
294#ifdef CONFIG_FSL_DIU_FB
295#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
296#else
297#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
298#endif
299
300/* FPGA */
301#define CONFIG_ARIA_FPGA 1
302
303/*
304 * Serial Port
305 */
306#define CONFIG_CONS_INDEX 1
Wolfgang Denk52568c32009-05-16 10:47:46 +0200307
308/*
309 * Serial console configuration
310 */
311#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
Marek Vasutbfb31272012-09-16 16:07:24 +0200312#define CONFIG_SYS_PSC3
Wolfgang Denk52568c32009-05-16 10:47:46 +0200313#if CONFIG_PSC_CONSOLE != 3
314#error CONFIG_PSC_CONSOLE must be 3
315#endif
316
317#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
318#define CONFIG_SYS_BAUDRATE_TABLE \
319 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
320
321#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
322#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
323#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
324#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
325
326#define CONFIG_CMDLINE_EDITING 1 /* command line history */
327/* Use the HUSH parser */
328#define CONFIG_SYS_HUSH_PARSER
329#ifdef CONFIG_SYS_HUSH_PARSER
Wolfgang Denk52568c32009-05-16 10:47:46 +0200330#endif
331
332/*
333 * PCI
334 */
335#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000336#define CONFIG_PCI_INDIRECT_BRIDGE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200337
338#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
339#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
340#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
341#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \
342 CONFIG_SYS_PCI_MEM_SIZE)
343#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
344#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
345#define CONFIG_SYS_PCI_IO_BASE 0x00000000
346#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
347#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
348
349#define CONFIG_PCI_PNP /* do pci plug-and-play */
350
351#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
352
353#endif
354
355/* I2C */
356#define CONFIG_HARD_I2C /* I2C with hardware support */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200357#define CONFIG_I2C_MULTI_BUS
Wolfgang Denk52568c32009-05-16 10:47:46 +0200358
359/* I2C speed and slave address */
360#define CONFIG_SYS_I2C_SPEED 100000
361#define CONFIG_SYS_I2C_SLAVE 0x7F
362#if 0
363#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
364#endif
365
366/*
367 * IIM - IC Identification Module
368 */
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000369#undef CONFIG_FSL_IIM
Wolfgang Denk52568c32009-05-16 10:47:46 +0200370
371/*
372 * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
373 * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
374 */
375#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
376#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
377#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
378#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
379
380/*
381 * Ethernet configuration
382 */
383#define CONFIG_MPC512x_FEC 1
Wolfgang Denk52568c32009-05-16 10:47:46 +0200384#define CONFIG_PHY_ADDR 0x17
385#define CONFIG_MII 1 /* MII PHY management */
386#define CONFIG_FEC_AN_TIMEOUT 1
387#define CONFIG_HAS_ETH0
388
389/*
390 * Environment
391 */
392#define CONFIG_ENV_IS_IN_FLASH 1
393/* This has to be a multiple of the flash sector size */
394#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
395 CONFIG_SYS_MONITOR_LEN)
396#define CONFIG_ENV_SIZE 0x2000
397#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */
398
399/* Address and size of Redundant Environment Sector */
400#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
401 CONFIG_ENV_SECT_SIZE)
402#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
403
404#define CONFIG_LOADS_ECHO 1
405#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
406
407#include <config_cmd_default.h>
408
409#define CONFIG_CMD_ASKENV
410#define CONFIG_CMD_DHCP
411#define CONFIG_CMD_EEPROM
412#undef CONFIG_CMD_FUSE
413#define CONFIG_CMD_I2C
414#undef CONFIG_CMD_IDE
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200415#define CONFIG_CMD_JFFS2
Wolfgang Denk52568c32009-05-16 10:47:46 +0200416#define CONFIG_CMD_MII
417#define CONFIG_CMD_NFS
418#define CONFIG_CMD_PING
419#define CONFIG_CMD_REGINFO
420
421#if defined(CONFIG_PCI)
422#define CONFIG_CMD_PCI
423#endif
424
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200425#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200426#define CONFIG_DOS_PARTITION
427#define CONFIG_MAC_PARTITION
428#define CONFIG_ISO_PARTITION
429#endif /* defined(CONFIG_CMD_IDE) */
430
431/*
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200432 * Dynamic MTD partition support
433 */
434#define CONFIG_CMD_MTDPARTS
435#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
436#define CONFIG_FLASH_CFI_MTD
437#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand"
438
439/*
440 * NOR flash layout:
441 *
442 * F8000000 - FEAFFFFF 107 MiB User Data
443 * FEB00000 - FFAFFFFF 16 MiB Root File System
444 * FFB00000 - FFFEFFFF 4 MiB Linux Kernel
445 * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env
446 * FFFC0000 - FFFFFFFF 256 KiB Device Tree
447 *
448 * NAND flash layout: one big partition
449 */
450#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \
451 "16m(rootfs)," \
452 "4m(kernel)," \
453 "768k(u-boot)," \
454 "256k(dtb);" \
455 "mpc5121.nand:-(data)"
456
457/*
Wolfgang Denk52568c32009-05-16 10:47:46 +0200458 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
459 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
460 * is set to 0xFFFF, watchdog timeouts after about 64s. For details
461 * refer to chapter 36 of the MPC5121e Reference Manual.
462 */
463/* #define CONFIG_WATCHDOG */ /* enable watchdog */
464#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
465
466 /*
467 * Miscellaneous configurable options
468 */
469#define CONFIG_SYS_LONGHELP /* undef to save memory */
470#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200471
472#ifdef CONFIG_CMD_KGDB
473# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
474#else
475# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
476#endif
477
478/* Print Buffer Size */
479#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
480 sizeof(CONFIG_SYS_PROMPT) + 16)
481/* max number of command args */
482#define CONFIG_SYS_MAXARGS 32
483/* Boot Argument Buffer Size */
484#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
485
Wolfgang Denk52568c32009-05-16 10:47:46 +0200486/*
487 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700488 * have to be in the first 256 MB of memory, since this is
Wolfgang Denk52568c32009-05-16 10:47:46 +0200489 * the maximum mapped by the Linux kernel during initialization.
490 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700491#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200492
493/* Cache Configuration */
494#define CONFIG_SYS_DCACHE_SIZE 32768
495#define CONFIG_SYS_CACHELINE_SIZE 32
496#ifdef CONFIG_CMD_KGDB
497#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
498#endif
499
500#define CONFIG_SYS_HID0_INIT 0x000000000
501#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
502 HID0_ICE)
503#define CONFIG_SYS_HID2 HID2_HBE
504
505#define CONFIG_HIGH_BATS 1 /* High BATs supported */
506
Wolfgang Denk52568c32009-05-16 10:47:46 +0200507#ifdef CONFIG_CMD_KGDB
508#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200509#endif
510
511/*
512 * Environment Configuration
513 */
514#define CONFIG_ENV_OVERWRITE
515#define CONFIG_TIMESTAMP
516
517#define CONFIG_HOSTNAME aria
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000518#define CONFIG_BOOTFILE "aria/uImage"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000519#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
Wolfgang Denk52568c32009-05-16 10:47:46 +0200520
521#define CONFIG_LOADADDR 400000 /* default load addr */
522
523#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
524#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
525
526#define CONFIG_BAUDRATE 115200
527
528#define CONFIG_PREBOOT "echo;" \
529 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
530 "echo"
531
532#define CONFIG_EXTRA_ENV_SETTINGS \
533 "u-boot_addr_r=200000\0" \
534 "kernel_addr_r=600000\0" \
535 "fdt_addr_r=880000\0" \
536 "ramdisk_addr_r=900000\0" \
537 "u-boot_addr=FFF00000\0" \
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200538 "kernel_addr=FFB00000\0" \
539 "fdt_addr=FFFC0000\0" \
540 "ramdisk_addr=FEB00000\0" \
Wolfgang Denk52568c32009-05-16 10:47:46 +0200541 "ramdiskfile=aria/uRamdisk\0" \
542 "u-boot=aria/u-boot.bin\0" \
543 "fdtfile=aria/aria.dtb\0" \
544 "netdev=eth0\0" \
545 "consdev=ttyPSC0\0" \
546 "nfsargs=setenv bootargs root=/dev/nfs rw " \
547 "nfsroot=${serverip}:${rootpath}\0" \
548 "ramargs=setenv bootargs root=/dev/ram rw\0" \
549 "addip=setenv bootargs ${bootargs} " \
550 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
551 ":${hostname}:${netdev}:off panic=1\0" \
552 "addtty=setenv bootargs ${bootargs} " \
553 "console=${consdev},${baudrate}\0" \
554 "flash_nfs=run nfsargs addip addtty;" \
555 "bootm ${kernel_addr} - ${fdt_addr}\0" \
556 "flash_self=run ramargs addip addtty;" \
557 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
558 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
559 "tftp ${fdt_addr_r} ${fdtfile};" \
560 "run nfsargs addip addtty;" \
561 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
562 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
563 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
564 "tftp ${fdt_addr_r} ${fdtfile};" \
565 "run ramargs addip addtty;" \
566 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
567 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
568 "update=protect off ${u-boot_addr} +${filesize};" \
569 "era ${u-boot_addr} +${filesize};" \
570 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
571 "upd=run load update\0" \
572 ""
573
574#define CONFIG_BOOTCOMMAND "run flash_self"
575
576#define CONFIG_OF_LIBFDT 1
577#define CONFIG_OF_BOARD_SETUP 1
578#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
579
580#define OF_CPU "PowerPC,5121@0"
581#define OF_SOC_COMPAT "fsl,mpc5121-immr"
582#define OF_TBCLK (bd->bi_busfreq / 4)
583#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
584
585/*-----------------------------------------------------------------------
586 * IDE/ATA stuff
587 *-----------------------------------------------------------------------
588 */
589
590#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
591#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
592#undef CONFIG_IDE_LED /* LED for IDE not supported */
593
594#define CONFIG_IDE_RESET /* reset for IDE supported */
595#define CONFIG_IDE_PREINIT
596
597#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
598#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */
599
600#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
601#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
602
603/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
604#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
605
606/* Offset for normal register accesses */
607#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
608
609/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
610#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
611
612/* Interval between registers */
613#define CONFIG_SYS_ATA_STRIDE 4
614
615#define ATA_BASE_ADDR get_pata_base()
616
617/*
618 * Control register bit definitions
619 */
620#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
621#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
622#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
623#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
624#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
625#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
626#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
627#define FSL_ATA_CTRL_IORDY_EN 0x01000000
628
Anatolij Gustschine5f53862013-02-08 00:03:45 +0000629/* Clocks in use */
630#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
631 CLOCK_SCCR1_LPC_EN | \
632 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
633 CLOCK_SCCR1_PSCFIFO_EN | \
634 CLOCK_SCCR1_DDR_EN | \
635 CLOCK_SCCR1_FEC_EN | \
636 CLOCK_SCCR1_NFC_EN | \
637 CLOCK_SCCR1_PATA_EN | \
638 CLOCK_SCCR1_PCI_EN | \
639 CLOCK_SCCR1_TPR_EN)
640
641#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
642 CLOCK_SCCR2_SPDIF_EN | \
643 CLOCK_SCCR2_DIU_EN | \
644 CLOCK_SCCR2_I2C_EN)
645
Wolfgang Denk52568c32009-05-16 10:47:46 +0200646#endif /* __CONFIG_H */