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Stefan Roese88dc4092018-08-16 15:27:31 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
4 */
5
6#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H
7#define __CONFIG_GARDENA_SMART_GATEWAY_H
8
Stefan Roese88dc4092018-08-16 15:27:31 +02009/* RAM */
Tom Riniaa6e94d2022-11-16 13:10:37 -050010#define CFG_SYS_SDRAM_BASE 0x80000000
Stefan Roese88dc4092018-08-16 15:27:31 +020011
Tom Rini65cc0e22022-11-16 13:10:41 -050012#define CFG_SYS_INIT_SP_OFFSET 0x400000
Stefan Roese88dc4092018-08-16 15:27:31 +020013
Weijie Gao757cbbe2020-04-21 09:28:48 +020014/* SPL */
Stefan Roese88dc4092018-08-16 15:27:31 +020015
Tom Rini65cc0e22022-11-16 13:10:41 -050016#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
Weijie Gao757cbbe2020-04-21 09:28:48 +020017
18/* Dummy value */
Tom Rini65cc0e22022-11-16 13:10:41 -050019#define CFG_SYS_UBOOT_BASE 0
Weijie Gao757cbbe2020-04-21 09:28:48 +020020
21/* Serial SPL */
Simon Glass2a736062021-08-08 12:20:12 -060022#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
Tom Rini91092132022-11-16 13:10:28 -050023#define CFG_SYS_NS16550_CLK 40000000
24#define CFG_SYS_NS16550_COM1 0xb0000c00
Weijie Gao757cbbe2020-04-21 09:28:48 +020025#endif
26
Stefan Roese88dc4092018-08-16 15:27:31 +020027/* UART */
Tom Rini65cc0e22022-11-16 13:10:41 -050028#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
Weijie Gao443a2062019-09-25 17:45:42 +080029 230400, 460800, 921600 }
Stefan Roese88dc4092018-08-16 15:27:31 +020030
31/* RAM */
Stefan Roese88dc4092018-08-16 15:27:31 +020032
Stefan Roese88dc4092018-08-16 15:27:31 +020033/* Environment settings */
Stefan Roese88dc4092018-08-16 15:27:31 +020034
Stefan Roese88dc4092018-08-16 15:27:31 +020035#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */