Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ |
| 2 | * |
| 3 | * Copyright (c) 2021 Linumiz |
| 4 | * Author: Navin Sankar Velliangiri <navin@linumiz.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef _NPI_IMX6ULL_H |
| 8 | #define _NPI_IMX6ULL_H |
| 9 | |
| 10 | #include <linux/sizes.h> |
| 11 | #include "mx6_common.h" |
| 12 | |
Tom Rini | 6cc0454 | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 13 | #define CFG_SYS_FSL_USDHC_NUM 1 |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 14 | |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 15 | /* Console configs */ |
| 16 | #define CONFIG_MXC_UART_BASE UART1_BASE |
| 17 | |
| 18 | /* MMC Configs */ |
Tom Rini | 6cc0454 | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 19 | #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 20 | |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 21 | /* Physical Memory Map */ |
| 22 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
| 23 | |
Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 24 | #define CFG_SYS_SDRAM_BASE PHYS_SDRAM |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 25 | #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| 26 | #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 27 | |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 28 | /* NAND */ |
Tom Rini | 4e59094 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 29 | #define CFG_SYS_NAND_BASE 0x40000000 |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 30 | |
| 31 | /* USB Configs */ |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 32 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
| 33 | #define CONFIG_MXC_USB_FLAGS 0 |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 34 | |
| 35 | #ifdef CONFIG_CMD_NET |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 36 | #define CONFIG_FEC_MXC_PHYADDR 0x1 |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 37 | #endif |
| 38 | |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 39 | #define CONFIG_FEC_ENET_DEV 1 |
| 40 | |
| 41 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 42 | "console=ttymxc0,115200n8\0" \ |
| 43 | "image=zImage\0" \ |
| 44 | "fdtfile=imx6ull-seeed-npi-dev-board.dtb\0" \ |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 45 | "fdt_addr_r=0x82000000\0" \ |
| 46 | "kernel_addr_r=0x81000000\0" \ |
| 47 | "pxefile_addr_r=0x87100000\0" \ |
| 48 | "ramdisk_addr_r=0x82100000\0" \ |
| 49 | "scriptaddr=0x87000000\0" \ |
| 50 | "root=/dev/mmcblk0p2 rootwait\0" \ |
| 51 | BOOTENV |
| 52 | |
| 53 | #define BOOT_TARGET_DEVICES(func) \ |
| 54 | func(MMC, mmc, 0) \ |
Pali Rohár | e6ca148 | 2022-05-31 10:32:36 +0200 | [diff] [blame] | 55 | func(UBIFS, ubifs, 0, UBI, boot) \ |
Navin Sankar Velliangiri | a3a0bc8 | 2021-05-18 09:03:20 +0530 | [diff] [blame] | 56 | func(PXE, pxe, na) \ |
| 57 | func(DHCP, dhcp, na) |
| 58 | |
| 59 | #include <config_distro_bootcmd.h> |
| 60 | |
| 61 | #endif /* _NPI_IMX6ULL_H */ |