| Holger Brunck | 468ba8d | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| Holger Brunck | 5d57dfa | 2020-10-08 12:27:22 +0200 | [diff] [blame] | 3 | * Copyright (C) 2017-2020 Hitachi Power Grids |
| Holger Brunck | 468ba8d | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 4 | * |
| 5 | */ |
| 6 | #ifndef __CONFIG_SOCFPGA_SECU1_H__ |
| 7 | #define __CONFIG_SOCFPGA_SECU1_H__ |
| 8 | |
| 9 | #include <asm/arch/base_addr_ac5.h> |
| Holger Brunck | 468ba8d | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 10 | |
| Holger Brunck | 468ba8d | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 11 | /* Eternal oscillator */ |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 12 | #define CFG_SYS_TIMER_RATE 40000000 |
| Holger Brunck | 468ba8d | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 13 | |
| 14 | /* Memory configurations */ |
| 15 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */ |
| 16 | |
| 17 | /* |
| 18 | * We use bootcounter in i2c nvram of the RTC (0x68) |
| 19 | * The offset fopr the bootcounter is 0x9e, which are |
| 20 | * the last two bytes of the 128 bytes large NVRAM in the |
| 21 | * RTC which begin at address 0x20 |
| 22 | */ |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 23 | #define CFG_SYS_I2C_RTC_ADDR 0x68 |
| Holger Brunck | 468ba8d | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 24 | |
| Holger Brunck | 468ba8d | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 25 | /* The rest of the configuration is shared */ |
| 26 | #include <configs/socfpga_common.h> |
| 27 | |
| Holger Brunck | 468ba8d | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 28 | #endif /* __CONFIG_SOCFPGA_SECU1_H__ */ |