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Jerome Brunet17b7efe2019-02-08 16:23:20 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7#include <common.h>
Simon Glass9b4a2052019-12-28 10:45:05 -07008#include <init.h>
Jerome Brunet17b7efe2019-02-08 16:23:20 +01009#include <asm/arch/boot.h>
10#include <asm/arch/eth.h>
11#include <asm/arch/g12a.h>
12#include <asm/arch/mem.h>
Neil Armstrong4ba46d82019-08-30 14:09:26 +020013#include <asm/arch/meson-vpu.h>
Jerome Brunet17b7efe2019-02-08 16:23:20 +010014#include <asm/io.h>
15#include <asm/armv8/mmu.h>
16#include <linux/sizes.h>
Neil Armstrong92d911b2019-02-19 14:21:04 +010017#include <usb.h>
18#include <linux/usb/otg.h>
19#include <asm/arch/usb.h>
20#include <usb/dwc2_udc.h>
Jerome Brunet17b7efe2019-02-08 16:23:20 +010021#include <phy.h>
Neil Armstrong92d911b2019-02-19 14:21:04 +010022#include <clk.h>
Jerome Brunet17b7efe2019-02-08 16:23:20 +010023
24DECLARE_GLOBAL_DATA_PTR;
25
26int meson_get_boot_device(void)
27{
28 return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
29}
30
31/* Configure the reserved memory zones exported by the secure registers
32 * into EFI and DTB reserved memory entries.
33 */
34void meson_init_reserved_memory(void *fdt)
35{
36 u64 bl31_size, bl31_start;
37 u64 bl32_size, bl32_start;
38 u32 reg;
39
40 /*
41 * Get ARM Trusted Firmware reserved memory zones in :
42 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
43 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
44 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
45 */
46 reg = readl(G12A_AO_SEC_GP_CFG3);
47
48 bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
49 >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
50 bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
51
52 bl31_start = readl(G12A_AO_SEC_GP_CFG5);
53 bl32_start = readl(G12A_AO_SEC_GP_CFG4);
54
55 /* Add BL31 reserved zone */
56 if (bl31_start && bl31_size)
57 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
58
59 /* Add BL32 reserved zone */
60 if (bl32_start && bl32_size)
61 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
Neil Armstrong4ba46d82019-08-30 14:09:26 +020062
63#if defined(CONFIG_VIDEO_MESON)
64 meson_vpu_rsv_fb(fdt);
65#endif
Jerome Brunet17b7efe2019-02-08 16:23:20 +010066}
67
68phys_size_t get_effective_memsize(void)
69{
70 /* Size is reported in MiB, convert it in bytes */
Neil Armstrong5e5db092019-07-22 11:32:50 +020071 return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
72 >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
Jerome Brunet17b7efe2019-02-08 16:23:20 +010073}
74
75static struct mm_region g12a_mem_map[] = {
76 {
77 .virt = 0x0UL,
78 .phys = 0x0UL,
Neil Armstrong5e5db092019-07-22 11:32:50 +020079 .size = 0xf5000000UL,
Jerome Brunet17b7efe2019-02-08 16:23:20 +010080 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
81 PTE_BLOCK_INNER_SHARE
82 }, {
Neil Armstrong5e5db092019-07-22 11:32:50 +020083 .virt = 0xf5000000UL,
84 .phys = 0xf5000000UL,
85 .size = 0x0b000000UL,
Jerome Brunet17b7efe2019-02-08 16:23:20 +010086 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
87 PTE_BLOCK_NON_SHARE |
88 PTE_BLOCK_PXN | PTE_BLOCK_UXN
89 }, {
90 /* List terminator */
91 0,
92 }
93};
94
95struct mm_region *mem_map = g12a_mem_map;
96
97static void g12a_enable_external_mdio(void)
98{
99 writel(0x0, ETH_PHY_CNTL2);
100}
101
102static void g12a_enable_internal_mdio(void)
103{
104 /* Fire up the PHY PLL */
105 writel(0x29c0040a, ETH_PLL_CNTL0);
106 writel(0x927e0000, ETH_PLL_CNTL1);
107 writel(0xac5f49e5, ETH_PLL_CNTL2);
108 writel(0x00000000, ETH_PLL_CNTL3);
109 writel(0x00000000, ETH_PLL_CNTL4);
110 writel(0x20200000, ETH_PLL_CNTL5);
111 writel(0x0000c002, ETH_PLL_CNTL6);
112 writel(0x00000023, ETH_PLL_CNTL7);
113 writel(0x39c0040a, ETH_PLL_CNTL0);
114 writel(0x19c0040a, ETH_PLL_CNTL0);
115
116 /* Select the internal MDIO */
117 writel(0x33000180, ETH_PHY_CNTL0);
118 writel(0x00074043, ETH_PHY_CNTL1);
119 writel(0x00000260, ETH_PHY_CNTL2);
120}
121
122/* Configure the Ethernet MAC with the requested interface mode
123 * with some optional flags.
124 */
125void meson_eth_init(phy_interface_t mode, unsigned int flags)
126{
127 switch (mode) {
128 case PHY_INTERFACE_MODE_RGMII:
129 case PHY_INTERFACE_MODE_RGMII_ID:
130 case PHY_INTERFACE_MODE_RGMII_RXID:
131 case PHY_INTERFACE_MODE_RGMII_TXID:
132 /* Set RGMII mode */
133 setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
134 G12A_ETH_REG_0_TX_PHASE(1) |
135 G12A_ETH_REG_0_TX_RATIO(4) |
136 G12A_ETH_REG_0_PHY_CLK_EN |
137 G12A_ETH_REG_0_CLK_EN);
Neil Armstrong5e5db092019-07-22 11:32:50 +0200138 g12a_enable_external_mdio();
Jerome Brunet17b7efe2019-02-08 16:23:20 +0100139 break;
140
141 case PHY_INTERFACE_MODE_RMII:
142 /* Set RMII mode */
143 out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
144 G12A_ETH_REG_0_INVERT_RMII_CLK |
145 G12A_ETH_REG_0_CLK_EN);
146
147 /* Use G12A RMII Internal PHY */
148 if (flags & MESON_USE_INTERNAL_RMII_PHY)
149 g12a_enable_internal_mdio();
150 else
151 g12a_enable_external_mdio();
152
153 break;
154
155 default:
156 printf("Invalid Ethernet interface mode\n");
157 return;
158 }
159
160 /* Enable power gate */
161 clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
162}
Neil Armstrong92d911b2019-02-19 14:21:04 +0100163
164#if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
165 CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
166static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
167
168int board_usb_init(int index, enum usb_init_type init)
169{
170 struct fdtdec_phandle_args args;
171 const void *blob = gd->fdt_blob;
172 int node, dwc2_node;
173 struct udevice *dev, *clk_dev;
174 struct clk clk;
175 int ret;
176
177 /* find the usb glue node */
178 node = fdt_node_offset_by_compatible(blob, -1,
179 "amlogic,meson-g12a-usb-ctrl");
180 if (node < 0) {
181 debug("Not found usb-control node\n");
182 return -ENODEV;
183 }
184
185 if (!fdtdec_get_is_enabled(blob, node)) {
186 debug("usb is disabled in the device tree\n");
187 return -ENODEV;
188 }
189
190 ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
191 if (ret) {
192 debug("Not found usb-control device\n");
193 return ret;
194 }
195
196 /* find the dwc2 node */
197 dwc2_node = fdt_node_offset_by_compatible(blob, node,
198 "amlogic,meson-g12a-usb");
199 if (dwc2_node < 0) {
200 debug("Not found dwc2 node\n");
201 return -ENODEV;
202 }
203
204 if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
205 debug("dwc2 is disabled in the device tree\n");
206 return -ENODEV;
207 }
208
209 meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
210 if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
211 debug("usbotg: can't get base address\n");
212 return -ENODATA;
213 }
214
215 /* Enable clock */
216 ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
217 "#clock-cells", 0, 0, &args);
218 if (ret) {
219 debug("usbotg has no clocks defined in the device tree\n");
220 return ret;
221 }
222
223 ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
224 if (ret)
225 return ret;
226
227 if (args.args_count != 1) {
228 debug("Can't find clock ID in the device tree\n");
229 return -ENODATA;
230 }
231
232 clk.dev = clk_dev;
233 clk.id = args.args[0];
234
235 ret = clk_enable(&clk);
236 if (ret) {
237 debug("Failed to enable usbotg clock\n");
238 return ret;
239 }
240
241 meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
242 "g-rx-fifo-size", 0);
243 meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
244 "g-np-tx-fifo-size", 0);
245 meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
246 "g-tx-fifo-size", 0);
247
248 /* Switch to peripheral mode */
249 ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
250 if (ret)
251 return ret;
252
253 return dwc2_udc_probe(&meson_g12a_dwc2_data);
254}
255
256int board_usb_cleanup(int index, enum usb_init_type init)
257{
258 const void *blob = gd->fdt_blob;
259 struct udevice *dev;
260 int node;
261 int ret;
262
263 /* find the usb glue node */
264 node = fdt_node_offset_by_compatible(blob, -1,
265 "amlogic,meson-g12a-usb-ctrl");
266 if (node < 0)
267 return -ENODEV;
268
269 if (!fdtdec_get_is_enabled(blob, node))
270 return -ENODEV;
271
272 ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
273 if (ret)
274 return ret;
275
276 /* Switch to OTG mode */
277 ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_HOST);
278 if (ret)
279 return ret;
280
281 return 0;
282}
283#endif