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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 0aeb01d512772a88e0cbe2fa8654daf1b0136189 / . / board / siemens / SMN42 / lowlevel_init.S
blob: 44e209b5de97c6052de28e1d6cb0fec3d9a9b3dc [file] [log] [blame]
Peter Pearse65fb6a62007-05-09 11:42:44 +0100[diff] [blame]1/*
2 * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
3 *
4 * Slight modifications made to support the SMN42 board from Siemens.
5 * 2007 Gary Jennejohn garyj@denx.de
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <config.h>
24#include <version.h>
25#include <asm/arch/hardware.h>
26
27/* some parameters for the board */
28/* setting up the CPU-internal memory */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]29#define SRAM_START 0x40000000
30#define SRAM_SIZE 0x00004000
31#define BCFG0_VALUE 0x1000ffef
32#define BCFG1_VALUE 0x10005D2F
33#define BCFG2_VALUE 0x10005D2F
Peter Pearse65fb6a62007-05-09 11:42:44 +0100[diff] [blame]34/*
35 * For P0.18 to set ZZ to the SRAMs to 1. Also set P0.2 (SCL) and P0.3 (SDA)
36 * for the bit-banger I2C driver correctly.
37 */
38#define IO0_VALUE 0x4000C
39
40_TEXT_BASE:
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame]41 .word CONFIG_SYS_TEXT_BASE
Peter Pearse65fb6a62007-05-09 11:42:44 +0100[diff] [blame]42MEMMAP_ADR:
43 .word MEMMAP
44BCFG0_ADR:
45 .word BCFG0
46_BCFG0_VALUE:
47 .word BCFG0_VALUE
48BCFG1_ADR:
49 .word BCFG1
50_BCFG1_VALUE:
51 .word BCFG1_VALUE
52BCFG2_ADR:
53 .word BCFG2
54_BCFG2_VALUE:
55 .word BCFG2_VALUE
56IO0DIR_ADR:
57 .word IO0DIR
58_IO0DIR_VALUE:
59 .word IO0_VALUE
60IO0SET_ADR:
61 .word IO0SET
62_IO0SET_VALUE:
63 .word IO0_VALUE
64PINSEL2_ADR:
65 .word PINSEL2
66PINSEL2_MASK:
67 .word 0x00000000
68PINSEL2_VALUE:
69 .word 0x0F804914
70
71.extern _start
72
73.globl lowlevel_init
74lowlevel_init:
75 /* set up memory control register for bank 0 */
76 ldr r0, _BCFG0_VALUE
77 ldr r1, BCFG0_ADR
78 str r0, [r1]
79
80 /* set up memory control register for bank 1 */
81 ldr r0, _BCFG1_VALUE
82 ldr r1, BCFG1_ADR
83 str r0, [r1]
84
85 /* set up memory control register for bank 2 */
86 ldr r0, _BCFG2_VALUE
87 ldr r1, BCFG2_ADR
88 str r0, [r1]
89
90 /* set IO0DIR to make P0.2, P0.3 and P0.18 outputs */
91 ldr r0, _IO0DIR_VALUE
92 ldr r1, IO0DIR_ADR
93 str r0, [r1]
94
95 /* set P0.18 to 1 */
96 ldr r0, _IO0SET_VALUE
97 ldr r1, IO0SET_ADR
98 str r0, [r1]
99
100 /* set up PINSEL2 for bus-pins */
101 ldr r0, PINSEL2_ADR
102 ldr r1, [r0]
103 ldr r2, PINSEL2_MASK
104 ldr r3, PINSEL2_VALUE
105 and r1, r1, r2
106 orr r1, r1, r3
107 str r1, [r0]
108
109 /* move vectors to beginning of SRAM */
110 mov r2, #SRAM_START
111 mov r0, #0 /*_start*/
112 ldmneia r0!, {r3-r10}
113 stmneia r2!, {r3-r10}
114 ldmneia r0, {r3-r9}
115 stmneia r2, {r3-r9}
116
117 /* Set-up MEMMAP register, so vectors are taken from SRAM */
118 ldr r0, MEMMAP_ADR
119 mov r1, #0x02 /* vectors re-mapped to static RAM */
120 str r1, [r0]
121
122 /* everything is fine now */
123 mov pc, lr