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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 0b12843493cbeb59c7aee207b1b6d0c8daf24833 / . / board / amcc / makalu / makalu.c
blob: a6ad2a1ba6086fcccf7ec5bfd52064e8f4080be2 [file] [log] [blame]
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]6 */
7
8#include <common.h>
Stefan Roeseb36df562010-09-09 19:18:00 +0200[diff] [blame]9#include <asm/ppc4xx.h>
10#include <asm/ppc405.h>
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]11#include <libfdt.h>
12#include <asm/processor.h>
Stefan Roese09887762010-09-16 14:30:37 +0200[diff] [blame]13#include <asm/ppc4xx-gpio.h>
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100[diff] [blame]14#include <asm/io.h>
Wolfgang Denk6eb3fb12008-01-13 16:07:44 +0100[diff] [blame]15#include <fdt_support.h>
Stefan Roese06dfaee2009-10-02 14:35:16 +0200[diff] [blame]16#include <asm/errno.h>
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]17
18#if defined(CONFIG_PCI)
19#include <pci.h>
20#include <asm/4xx_pcie.h>
21#endif
22
23DECLARE_GLOBAL_DATA_PTR;
24
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]25extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]26
27/*
28 * Board early initialization function
29 */
30int board_early_init_f (void)
31{
Stefan Roese7cfc12a2007-12-08 14:47:34 +0100[diff] [blame]32 u32 val;
33
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]34 /*--------------------------------------------------------------------+
35 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
36 +--------------------------------------------------------------------+
37 +---------------------------------------------------------------------+
38 |Interrupt| Source | Pol. | Sensi.| Crit. |
39 +---------+-----------------------------------+-------+-------+-------+
40 | IRQ 00 | UART0 | High | Level | Non |
41 | IRQ 01 | UART1 | High | Level | Non |
42 | IRQ 02 | IIC0 | High | Level | Non |
43 | IRQ 03 | TBD | High | Level | Non |
44 | IRQ 04 | TBD | High | Level | Non |
45 | IRQ 05 | EBM | High | Level | Non |
46 | IRQ 06 | BGI | High | Level | Non |
47 | IRQ 07 | IIC1 | Rising| Edge | Non |
48 | IRQ 08 | SPI | High | Lvl/ed| Non |
49 | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
50 | IRQ 10 | MAL TX EOB | High | Level | Non |
51 | IRQ 11 | MAL RX EOB | High | Level | Non |
52 | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
53 | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
54 | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
55 | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
56 | IRQ 16 | PCIE0 AL | high | Level | Non |
57 | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
58 | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
59 | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
60 | IRQ 20 | PCIE0 TCR | High | Level | Non |
61 | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
62 | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
63 | IRQ 23 | Security EIP-94 | High | Level | Non |
64 | IRQ 24 | EMAC0 interrupt | High | Level | Non |
65 | IRQ 25 | EMAC1 interrupt | High | Level | Non |
66 | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
67 | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
68 | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
69 | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
70 | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
71 | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
72 |----------------------------------------------------------------------
73 | IRQ 32 | MAL Serr | High | Level | Non |
74 | IRQ 33 | MAL Txde | High | Level | Non |
75 | IRQ 34 | MAL Rxde | High | Level | Non |
76 | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
77 | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
78 | IRQ 37 | EBC | High |Lvl Edg| Non |
79 | IRQ 38 | NDFC | High | Level | Non |
80 | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
81 | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
82 | IRQ 41 | PCIE1 AL | high | Level | Non |
83 | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
84 | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
85 | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
86 | IRQ 45 | PCIE1 TCR | High | Level | Non |
87 | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
88 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
89 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
90 | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
91 | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
92 | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
93 | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
94 | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
95 | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
96 | IRQ 55 | Serial ROM | High | Level | Non |
97 | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
98 | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
99 | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
100 | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
101 | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
102 | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
103 | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
104 |----------------------------------------------------------------------
105 | IRQ 64 | PE0 AL | High | Level | Non |
106 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
107 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
108 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
109 | IRQ 68 | PE0 TCR | High | Level | Non |
110 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
111 | IRQ 70 | PE0 DCR Error | High | Level | Non |
112 | IRQ 71 | Reserved | N/A | N/A | Non |
113 | IRQ 72 | PE1 AL | High | Level | Non |
114 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
115 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
116 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
117 | IRQ 76 | PE1 TCR | High | Level | Non |
118 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
119 | IRQ 78 | PE1 DCR Error | High | Level | Non |
120 | IRQ 79 | Reserved | N/A | N/A | Non |
121 | IRQ 80 | PE2 AL | High | Level | Non |
122 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
123 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
124 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
125 | IRQ 84 | PE2 TCR | High | Level | Non |
126 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
127 | IRQ 86 | PE2 DCR Error | High | Level | Non |
128 | IRQ 87 | Reserved | N/A | N/A | Non |
129 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
130 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
131 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
132 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
133 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
134 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
135 | IRQ 94 | Reserved | N/A | N/A | Non |
136 | IRQ 95 | Reserved | N/A | N/A | Non |
137 |---------------------------------------------------------------------
138 +---------+-----------------------------------+-------+-------+------*/
139 /*--------------------------------------------------------------------+
140 | Initialise UIC registers. Clear all interrupts. Disable all
141 | interrupts.
142 | Set critical interrupt values. Set interrupt polarities. Set
143 | interrupt trigger levels. Make bit 0 High priority. Clear all
144 | interrupts again.
145 +-------------------------------------------------------------------*/
146
Stefan Roese952e7762009-09-24 09:55:50 +0200[diff] [blame]147 mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
148 mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
149 mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
150 mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
151 mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
152 mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
153 mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
154 mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]155
Stefan Roese952e7762009-09-24 09:55:50 +0200[diff] [blame]156 mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
157 mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
158 mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
159 mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
160 mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
161 mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
162 mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
163 mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]164
Stefan Roese952e7762009-09-24 09:55:50 +0200[diff] [blame]165 mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
166 mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]167 /* Except cascade UIC0 and UIC1 */
Stefan Roese952e7762009-09-24 09:55:50 +0200[diff] [blame]168 mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
169 mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
170 mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
171 mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
172 mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
173 mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]174
175 /*
176 * Note: Some cores are still in reset when the chip starts, so
177 * take them out of reset
178 */
179 mtsdr(SDR0_SRST, 0);
180
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100[diff] [blame]181 /* Reset PCIe slots */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]182 gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100[diff] [blame]183 udelay(100);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]184 gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100[diff] [blame]185
Stefan Roese7cfc12a2007-12-08 14:47:34 +0100[diff] [blame]186 /*
187 * Configure PFC (Pin Function Control) registers
188 * -> Enable USB
189 */
190 val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
191 mtsdr(SDR0_PFC1, val);
192
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]193 return 0;
194}
195
196int misc_init_r(void)
197{
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200[diff] [blame]198#ifdef CONFIG_ENV_IS_IN_FLASH
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]199 /* Monitor protection ON by default */
200 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]201 -CONFIG_SYS_MONITOR_LEN,
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]202 0xffffffff,
203 &flash_info[0]);
204#endif
205
206 return 0;
207}
208
209int checkboard (void)
210{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000[diff] [blame]211 char buf[64];
212 int i = getenv_f("serial#", buf, sizeof(buf));
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]213
214 printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
215
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000[diff] [blame]216 if (i > 0) {
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]217 puts(", serial# ");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000[diff] [blame]218 puts(buf);
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]219 }
220 putc('\n');
221
222 return (0);
223}