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Prabhakar Kushwaha7530d342012-04-24 20:17:15 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +00005 */
6
7/*
8 * BSC9131 RDB board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000014#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000015
16#ifdef CONFIG_SPIFLASH
17#define CONFIG_RAMBOOT_SPIFLASH
18#define CONFIG_SYS_RAMBOOT
19#define CONFIG_SYS_EXTRA_ENV_RELOC
20#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053021#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000022#endif
23
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +053024#ifdef CONFIG_NAND
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +053025#define CONFIG_SPL_INIT_MINIMAL
Prabhakar Kushwahafbe76ae2013-12-11 12:42:11 +053026#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +053027#define CONFIG_SPL_FLUSH_IMAGE
28#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
29
30#define CONFIG_SYS_TEXT_BASE 0x00201000
31#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
32#define CONFIG_SPL_MAX_SIZE 8192
33#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
34#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053035#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +053036#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
37#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
38#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
39#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000040#endif
41
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +053042#ifdef CONFIG_SPL_BUILD
43#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
44#else
45#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
46#endif
47
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000048/* High Level Configuration Options */
Ruchika Gupta737537e2014-10-15 11:35:31 +053049#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000050
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000051#define CONFIG_TSEC_ENET
52#define CONFIG_ENV_OVERWRITE
53
54#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
Priyanka Jain087cf442013-04-01 12:12:45 +053055#if defined(CONFIG_SYS_CLK_100)
56#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
57#else
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000058#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
Priyanka Jain087cf442013-04-01 12:12:45 +053059#endif
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000060
61#define CONFIG_HWCONFIG
62/*
63 * These can be toggled for performance analysis, otherwise use default.
64 */
65#define CONFIG_L2_CACHE /* toggle L2 cache */
66#define CONFIG_BTB /* enable branch predition */
67
68#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
69#define CONFIG_SYS_MEMTEST_END 0x01ffffff
70
71/* DDR Setup */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000072#undef CONFIG_SYS_DDR_RAW_TIMING
73#undef CONFIG_DDR_SPD
74#define CONFIG_SYS_SPD_BUS_NUM 0
75#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
76
77#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
78
79#ifndef __ASSEMBLY__
80extern unsigned long get_sdram_size(void);
81#endif
82#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
83#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
84#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
85
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +000086#define CONFIG_DIMM_SLOTS_PER_CTLR 1
87#define CONFIG_CHIP_SELECTS_PER_CTRL 1
88
89#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
90#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
91#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
92
93#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
94#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
95#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
96#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
97
98#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
99#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
100#define CONFIG_SYS_DDR_RCW_1 0x00000000
101#define CONFIG_SYS_DDR_RCW_2 0x00000000
102#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
103#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
104#define CONFIG_SYS_DDR_TIMING_4 0x00000001
105#define CONFIG_SYS_DDR_TIMING_5 0x02401400
106
107#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
108#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
109#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
110#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
111#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
112#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
113#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
114#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
115#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
116
117/*
118 * Base addresses -- Note these are effective addresses where the
119 * actual resources get mapped (not physical addresses)
120 */
121/* relocated CCSRBAR */
122#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
123#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
124
125#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
126 /* CONFIG_SYS_IMMR */
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530127/* DSP CCSRBAR */
128#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
129#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000130
131/*
132 * Memory map
133 *
134 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
135 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530136 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000137 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
138 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
139 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
140 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530141 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000142 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
143 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
144 *
145 */
146
147/*
148 * IFC Definitions
149 */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000150
151/* NAND Flash on IFC */
152#define CONFIG_SYS_NAND_BASE 0xff800000
153#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
154
155#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
156 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
157 | CSPR_MSEL_NAND /* MSEL = NAND */ \
158 | CSPR_V)
159#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
160
161#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
162 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
163 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
164 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
165 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
166 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
167 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
168
169/* NAND Flash Timing Params */
Prabhakar Kushwaha4544fd22013-09-10 17:33:12 +0530170#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
171 | FTIM0_NAND_TWP(0x05) \
172 | FTIM0_NAND_TWCHT(0x02) \
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000173 | FTIM0_NAND_TWH(0x04))
Prabhakar Kushwaha4544fd22013-09-10 17:33:12 +0530174#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
175 | FTIM1_NAND_TWBE(0x1E) \
176 | FTIM1_NAND_TRR(0x07) \
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000177 | FTIM1_NAND_TRP(0x05))
178#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
179 | FTIM2_NAND_TREH(0x04) \
Prabhakar Kushwaha4544fd22013-09-10 17:33:12 +0530180 | FTIM2_NAND_TWHRE(0x11))
181#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000182
183#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
184#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000185#define CONFIG_CMD_NAND
186#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
187
188#define CONFIG_SYS_NAND_DDR_LAW 11
189
190/* Set up IFC registers for boot location NAND */
191#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
192#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
193#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
194#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
195#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
196#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
197#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
198
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000199#define CONFIG_SYS_INIT_RAM_LOCK
200#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
York Sunb39d1212016-04-06 13:22:10 -0700201#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000202
York Sunb39d1212016-04-06 13:22:10 -0700203#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000204 - GENERATED_GBL_DATA_SIZE)
205#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
206
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530207#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000208#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
209
210/* Serial Port */
211#define CONFIG_CONS_INDEX 1
212#undef CONFIG_SERIAL_SOFTWARE_FIFO
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000213#define CONFIG_SYS_NS16550_SERIAL
214#define CONFIG_SYS_NS16550_REG_SIZE 1
215#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +0530216#ifdef CONFIG_SPL_BUILD
217#define CONFIG_NS16550_MIN_FUNCTIONS
218#endif
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000219
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000220#define CONFIG_SYS_BAUDRATE_TABLE \
221 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
222
223#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
224
Heiko Schocher00f792e2012-10-24 13:48:22 +0200225#define CONFIG_SYS_I2C
226#define CONFIG_SYS_I2C_FSL
227#define CONFIG_SYS_FSL_I2C_SPEED 400000
228#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
229#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000230
231/* I2C EEPROM */
232#define CONFIG_CMD_EEPROM
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000233#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
234#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
235#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
236
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000237/* eSPI - Enhanced SPI */
238#ifdef CONFIG_FSL_ESPI
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000239#define CONFIG_SF_DEFAULT_SPEED 10000000
240#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
241#endif
242
243#if defined(CONFIG_TSEC_ENET)
244
245#define CONFIG_MII /* MII PHY management */
246#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
247#define CONFIG_TSEC1 1
248#define CONFIG_TSEC1_NAME "eTSEC1"
249#define CONFIG_TSEC2 1
250#define CONFIG_TSEC2_NAME "eTSEC2"
251
252#define TSEC1_PHY_ADDR 0
253#define TSEC2_PHY_ADDR 3
254
255#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
256#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
257
258#define TSEC1_PHYIDX 0
259
260#define TSEC2_PHYIDX 0
261
262#define CONFIG_ETHPRIME "eTSEC1"
263
264#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
265
266#endif /* CONFIG_TSEC_ENET */
267
268/*
269 * Environment
270 */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000271#if defined(CONFIG_RAMBOOT_SPIFLASH)
272#define CONFIG_ENV_IS_IN_SPI_FLASH
273#define CONFIG_ENV_SPI_BUS 0
274#define CONFIG_ENV_SPI_CS 0
275#define CONFIG_ENV_SPI_MAX_HZ 10000000
276#define CONFIG_ENV_SPI_MODE 0
277#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
278#define CONFIG_ENV_SECT_SIZE 0x10000
279#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +0530280#elif defined(CONFIG_NAND)
281#define CONFIG_ENV_IS_IN_NAND
282#define CONFIG_SYS_EXTRA_ENV_RELOC
283#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530284#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +0530285#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
286#elif defined(CONFIG_SYS_RAMBOOT)
287#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000288#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +0530289#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000290#endif
291
292#define CONFIG_LOADS_ECHO /* echo on for serial download */
293#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
294
295/*
296 * Command line configuration.
297 */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000298#define CONFIG_CMD_ERRATA
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000299#define CONFIG_CMD_IRQ
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000300#define CONFIG_CMD_REGINFO
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000301
302/*
303 * Miscellaneous configurable options
304 */
305#define CONFIG_SYS_LONGHELP /* undef to save memory */
306#define CONFIG_CMDLINE_EDITING /* Command-line editing */
307#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
308#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000309
310#if defined(CONFIG_CMD_KGDB)
311#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
312#else
313#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
314#endif
315#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
316 /* Print Buffer Size */
317#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
318#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000319
320/*
321 * For booting Linux, the board info and command line data
322 * have to be in the first 64 MB of memory, since this is
323 * the maximum mapped by the Linux kernel during initialization.
324 */
325#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
326#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
327
328#if defined(CONFIG_CMD_KGDB)
329#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000330#endif
331
Ruchika Gupta737537e2014-10-15 11:35:31 +0530332/* Hash command with SHA acceleration supported in hardware */
333#ifdef CONFIG_FSL_CAAM
334#define CONFIG_CMD_HASH
335#define CONFIG_SHA_HW_ACCEL
336#endif
337
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000338#define CONFIG_USB_EHCI
339
340#ifdef CONFIG_USB_EHCI
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000341#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
342#define CONFIG_USB_EHCI_FSL
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000343#define CONFIG_HAS_FSL_DR_USB
344#endif
345
346/*
Ashish Kumar7ac1a242014-10-07 18:02:23 +0530347 * Dynamic MTD Partition support with mtdparts
348 */
349#define CONFIG_MTD_DEVICE
350#define CONFIG_MTD_PARTITIONS
351#define CONFIG_CMD_MTDPARTS
352#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
353#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
354 "8m(kernel),512k(dtb),-(fs)"
Ashish Kumar7ac1a242014-10-07 18:02:23 +0530355
356/*
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000357 * Environment Configuration
358 */
359
360#if defined(CONFIG_TSEC_ENET)
361#define CONFIG_HAS_ETH0
362#endif
363
364#define CONFIG_HOSTNAME BSC9131rdb
365#define CONFIG_ROOTPATH "/opt/nfsroot"
366#define CONFIG_BOOTFILE "uImage"
367#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
368
369#define CONFIG_BAUDRATE 115200
370
371#define CONFIG_EXTRA_ENV_SETTINGS \
372 "netdev=eth0\0" \
373 "uboot=" CONFIG_UBOOTPATH "\0" \
374 "loadaddr=1000000\0" \
375 "bootfile=uImage\0" \
376 "consoledev=ttyS0\0" \
377 "ramdiskaddr=2000000\0" \
378 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500379 "fdtaddr=1e00000\0" \
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000380 "fdtfile=bsc9131rdb.dtb\0" \
381 "bdev=sda1\0" \
382 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
Priyanka Jain1d2949a2013-04-04 14:40:32 +0530383 "bootm_size=0x37000000\0" \
384 "othbootargs=ramdisk_size=600000 " \
385 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
Prabhakar Kushwaha7530d342012-04-24 20:17:15 +0000386 "usbext2boot=setenv bootargs root=/dev/ram rw " \
387 "console=$consoledev,$baudrate $othbootargs; " \
388 "usb start;" \
389 "ext2load usb 0:4 $loadaddr $bootfile;" \
390 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
391 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
392 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
393
394#define CONFIG_RAMBOOTCOMMAND \
395 "setenv bootargs root=/dev/ram rw " \
396 "console=$consoledev,$baudrate $othbootargs; " \
397 "tftp $ramdiskaddr $ramdiskfile;" \
398 "tftp $loadaddr $bootfile;" \
399 "tftp $fdtaddr $fdtfile;" \
400 "bootm $loadaddr $ramdiskaddr $fdtaddr"
401
402#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
403
404#endif /* __CONFIG_H */