blob: 42f54ef759a02dd11ba27530979381b053c472a2 [file] [log] [blame]
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05301/*
2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Based on davinci_dvevm.h. Original Copyrights follow:
5 *
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05309 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * Board
16 */
Ben Gardiner3d248d32010-10-14 17:26:29 -040017#define CONFIG_DRIVER_TI_EMAC
Lad, Prabhakar63777662012-06-24 21:35:23 +000018/* check if direct NOR boot config is used */
19#ifndef CONFIG_DIRECT_NOR_BOOT
Stefano Babicd73a8a12010-11-11 15:38:02 +010020#define CONFIG_USE_SPIFLASH
Lad, Prabhakar63777662012-06-24 21:35:23 +000021#endif
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053022
23/*
24 * SoC Configuration
25 */
26#define CONFIG_MACH_DAVINCI_DA850_EVM
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053027#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
Christian Riesch52b0f872011-11-28 23:46:18 +000028#define CONFIG_SOC_DA850 /* TI DA850 SoC */
Christian Rieschb67d8812012-02-02 00:44:39 +000029#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053030#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
31#define CONFIG_SYS_OSCIN_FREQ 24000000
32#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
33#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053034
Lad, Prabhakar63777662012-06-24 21:35:23 +000035#ifdef CONFIG_DIRECT_NOR_BOOT
36#define CONFIG_ARCH_CPU_INIT
37#define CONFIG_DA8XX_GPIO
38#define CONFIG_SYS_TEXT_BASE 0x60000000
39#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
40#define CONFIG_DA850_LOWLEVEL
41#else
42#define CONFIG_SYS_TEXT_BASE 0xc1080000
43#endif
44
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053045/*
46 * Memory Info
47 */
48#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053049#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
50#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
Ben Gardiner97003752010-08-23 09:08:15 -040051#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053052
53/* memtest start addr */
54#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
55
56/* memtest will be run on 16MB */
57#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
58
59#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053060
Christian Riesch3d2c8e62011-12-09 09:47:37 +000061#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
62 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
63 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
64 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
65 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
66 DAVINCI_SYSCFG_SUSPSRC_I2C)
67
68/*
69 * PLL configuration
70 */
71#define CONFIG_SYS_DV_CLKMODE 0
72#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
73#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
74#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
75#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
76#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
77#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
78#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
79#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
80
81#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
82#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
83#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
84#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
85
86#define CONFIG_SYS_DA850_PLL0_PLLM 24
87#define CONFIG_SYS_DA850_PLL1_PLLM 21
88
89/*
90 * DDR2 memory configuration
91 */
92#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
93 DV_DDR_PHY_EXT_STRBEN | \
94 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
95
96#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
97 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
98 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
99 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
100 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
101 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
102 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
103 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
104
105/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
106#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
107
108#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
109 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
110 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
111 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
112 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
113 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
114 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
115 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
116 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
117
118#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
119 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
120 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
121 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
122 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
123 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
124 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
125 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
126
127#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
128#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
129
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530130/*
131 * Serial Driver info
132 */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530133#define CONFIG_SYS_NS16550_SERIAL
134#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
135#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
136#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
137#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
138#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530139
Stefano Babicd73a8a12010-11-11 15:38:02 +0100140#define CONFIG_SPI
Stefano Babicd73a8a12010-11-11 15:38:02 +0100141#define CONFIG_DAVINCI_SPI
142#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
143#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
144#define CONFIG_SF_DEFAULT_SPEED 30000000
145#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
146
Lad, Prabhakar42612102012-06-24 21:35:19 +0000147#ifdef CONFIG_USE_SPIFLASH
Lad, Prabhakar42612102012-06-24 21:35:19 +0000148#define CONFIG_SPL_SPI_LOAD
Lad, Prabhakar42612102012-06-24 21:35:19 +0000149#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
Peter Howard2a10f8b2014-12-17 12:14:36 +1100150#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
Lad, Prabhakar42612102012-06-24 21:35:19 +0000151#endif
152
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530153/*
154 * I2C Configuration
155 */
Vitaly Andrianove8459dc2014-04-04 13:16:52 -0400156#define CONFIG_SYS_I2C
157#define CONFIG_SYS_I2C_DAVINCI
158#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
159#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500160#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530161
162/*
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400163 * Flash & Environment
164 */
165#ifdef CONFIG_USE_NAND
166#undef CONFIG_ENV_IS_IN_FLASH
167#define CONFIG_NAND_DAVINCI
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400168#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
169#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
170#define CONFIG_ENV_SIZE (128 << 10)
171#define CONFIG_SYS_NAND_USE_FLASH_BBT
172#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
173#define CONFIG_SYS_NAND_PAGE_2K
174#define CONFIG_SYS_NAND_CS 3
175#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Eric Benard34fa0702013-04-22 05:55:00 +0000176#define CONFIG_SYS_NAND_MASK_CLE 0x10
177#define CONFIG_SYS_NAND_MASK_ALE 0x8
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400178#undef CONFIG_SYS_NAND_HW_ECC
179#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000180#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
181#define CONFIG_SYS_NAND_5_ADDR_CYCLE
182#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
183#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
184#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
185#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
186#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
187#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
188#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
189 CONFIG_SYS_NAND_U_BOOT_SIZE - \
190 CONFIG_SYS_MALLOC_LEN - \
191 GENERATED_GBL_DATA_SIZE)
192#define CONFIG_SYS_NAND_ECCPOS { \
193 24, 25, 26, 27, 28, \
194 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
195 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
196 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
197 59, 60, 61, 62, 63 }
198#define CONFIG_SYS_NAND_PAGE_COUNT 64
199#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
200#define CONFIG_SYS_NAND_ECCSIZE 512
201#define CONFIG_SYS_NAND_ECCBYTES 10
202#define CONFIG_SYS_NAND_OOBSIZE 64
Scott Wood6f2f01b2012-09-20 19:09:07 -0500203#define CONFIG_SPL_NAND_BASE
204#define CONFIG_SPL_NAND_DRIVERS
205#define CONFIG_SPL_NAND_ECC
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000206#define CONFIG_SPL_NAND_SIMPLE
207#define CONFIG_SPL_NAND_LOAD
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400208#endif
209
210/*
Ben Gardiner3d248d32010-10-14 17:26:29 -0400211 * Network & Ethernet Configuration
212 */
213#ifdef CONFIG_DRIVER_TI_EMAC
Ben Gardiner3d248d32010-10-14 17:26:29 -0400214#define CONFIG_MII
Ben Gardiner3d248d32010-10-14 17:26:29 -0400215#define CONFIG_BOOTP_DNS
216#define CONFIG_BOOTP_DNS2
217#define CONFIG_BOOTP_SEND_HOSTNAME
218#define CONFIG_NET_RETRY_COUNT 10
Ben Gardiner3d248d32010-10-14 17:26:29 -0400219#endif
220
Nagabhushana Netagunte1506b0a2011-09-03 22:18:32 -0400221#ifdef CONFIG_USE_NOR
222#define CONFIG_ENV_IS_IN_FLASH
223#define CONFIG_FLASH_CFI_DRIVER
224#define CONFIG_SYS_FLASH_CFI
225#define CONFIG_SYS_FLASH_PROTECTION
226#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
227#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
228#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
229#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
230#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
231#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
232#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
233 + 3)
234#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
235#endif
236
Stefano Babicd73a8a12010-11-11 15:38:02 +0100237#ifdef CONFIG_USE_SPIFLASH
238#undef CONFIG_ENV_IS_IN_FLASH
239#undef CONFIG_ENV_IS_IN_NAND
240#define CONFIG_ENV_IS_IN_SPI_FLASH
241#define CONFIG_ENV_SIZE (64 << 10)
Peter Howard2a10f8b2014-12-17 12:14:36 +1100242#define CONFIG_ENV_OFFSET (512 << 10)
Stefano Babicd73a8a12010-11-11 15:38:02 +0100243#define CONFIG_ENV_SECT_SIZE (64 << 10)
Stefano Babicd73a8a12010-11-11 15:38:02 +0100244#endif
245
Ben Gardiner3d248d32010-10-14 17:26:29 -0400246/*
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530247 * U-Boot general configuration
248 */
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400249#define CONFIG_MISC_INIT_R
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530250#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530251#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
252#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
253#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
254#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
255#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530256#define CONFIG_AUTO_COMPLETE
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530257#define CONFIG_CMDLINE_EDITING
258#define CONFIG_SYS_LONGHELP
259#define CONFIG_CRC32_VERIFY
260#define CONFIG_MX_CYCLIC
261
262/*
263 * Linux Information
264 */
Ben Gardiner59e0d612010-10-14 17:26:32 -0400265#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400266#define CONFIG_HWCONFIG /* enable hwconfig */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530267#define CONFIG_CMDLINE_TAG
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500268#define CONFIG_REVISION_TAG
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530269#define CONFIG_SETUP_MEMORY_TAGS
270#define CONFIG_BOOTARGS \
271 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400272#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530273
274/*
275 * U-Boot commands
276 */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530277#define CONFIG_CMD_ENV
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530278#define CONFIG_CMD_DIAG
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530279#define CONFIG_CMD_SAVES
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530280
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +0000281#ifdef CONFIG_CMD_BDI
282#define CONFIG_CLOCKS
283#endif
284
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530285#ifndef CONFIG_DRIVER_TI_EMAC
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530286#endif
287
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400288#ifdef CONFIG_USE_NAND
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400289#define CONFIG_CMD_NAND
Ben Gardiner771d0282010-10-14 17:26:27 -0400290
291#define CONFIG_CMD_MTDPARTS
292#define CONFIG_MTD_DEVICE
293#define CONFIG_MTD_PARTITIONS
294#define CONFIG_LZO
295#define CONFIG_RBTREE
Ben Gardiner771d0282010-10-14 17:26:27 -0400296#define CONFIG_CMD_UBIFS
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400297#endif
298
Stefano Babicd73a8a12010-11-11 15:38:02 +0100299#ifdef CONFIG_USE_SPIFLASH
Stefano Babicd73a8a12010-11-11 15:38:02 +0100300#endif
301
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530302#if !defined(CONFIG_USE_NAND) && \
303 !defined(CONFIG_USE_NOR) && \
304 !defined(CONFIG_USE_SPIFLASH)
305#define CONFIG_ENV_IS_NOWHERE
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530306#define CONFIG_ENV_SIZE (16 << 10)
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530307#undef CONFIG_CMD_ENV
308#endif
309
Lad, Prabhakar63777662012-06-24 21:35:23 +0000310#ifndef CONFIG_DIRECT_NOR_BOOT
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000311/* defines for SPL */
Tom Rini3f7f2412012-08-14 12:27:13 -0700312#define CONFIG_SPL_FRAMEWORK
313#define CONFIG_SPL_BOARD_INIT
314#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
315 CONFIG_SYS_MALLOC_LEN)
316#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Tom Rini3f7f2412012-08-14 12:27:13 -0700317#define CONFIG_SPL_SPI_LOAD
Sughosh Ganu6b873dc2012-02-02 00:44:41 +0000318#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000319#define CONFIG_SPL_STACK 0x8001ff00
320#define CONFIG_SPL_TEXT_BASE 0x80000000
Albert ARIBAUDb7b5f1a2013-04-12 05:14:32 +0000321#define CONFIG_SPL_MAX_FOOTPRINT 32768
Christian Riesch532d5312014-05-07 10:16:28 +0200322#define CONFIG_SPL_PAD_TO 32768
Lad, Prabhakar63777662012-06-24 21:35:23 +0000323#endif
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000324
325/* Load U-Boot Image From MMC */
326#ifdef CONFIG_SPL_MMC_LOAD
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000327#undef CONFIG_SPL_SPI_LOAD
328#endif
329
Heiko Schocherab86f722010-09-17 13:10:42 +0200330/* additions for new relocation code, must added to all boards */
Heiko Schocherab86f722010-09-17 13:10:42 +0200331#define CONFIG_SYS_SDRAM_BASE 0xc0000000
Lad, Prabhakar63777662012-06-24 21:35:23 +0000332
333#ifdef CONFIG_DIRECT_NOR_BOOT
334#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
335#else
Heiko Schocherab86f722010-09-17 13:10:42 +0200336#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200337 GENERATED_GBL_DATA_SIZE)
Lad, Prabhakar63777662012-06-24 21:35:23 +0000338#endif /* CONFIG_DIRECT_NOR_BOOT */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530339#endif /* __CONFIG_H */