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Rajeshwari Birje76dd9b62013-12-26 09:44:26 +05301/*
2 * Copyright (C) 2013 Samsung Electronics
3 *
4 * Configuration settings for the SAMSUNG EXYNOS5 board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
Simon Glass4c7bb1d2014-10-07 22:01:44 -06009#ifndef __CONFIG_EXYNOS5_COMMON_H
10#define __CONFIG_EXYNOS5_COMMON_H
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053011
Simon Glass5ea01ab2014-10-07 22:01:45 -060012#define CONFIG_EXYNOS5 /* Exynos5 Family */
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053013
Simon Glass5ea01ab2014-10-07 22:01:45 -060014#include "exynos-common.h"
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053015
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053016#define CONFIG_EXYNOS_SPL
17
Inha Songf44ef7d2015-03-13 17:48:35 +090018#ifdef FTRACE
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053019#define CONFIG_TRACE
20#define CONFIG_CMD_TRACE
21#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
22#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
23#define CONFIG_TRACE_EARLY
24#define CONFIG_TRACE_EARLY_ADDR 0x50000000
Inha Songf44ef7d2015-03-13 17:48:35 +090025#endif
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053026
27/* Enable ACE acceleration for SHA1 and SHA256 */
28#define CONFIG_EXYNOS_ACE_SHA
29#define CONFIG_SHA_HW_ACCEL
30
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053031/* Power Down Modes */
32#define S5P_CHECK_SLEEP 0x00000BAD
33#define S5P_CHECK_DIDLE 0xBAD00000
34#define S5P_CHECK_LPA 0xABAD0000
35
36/* Offset for inform registers */
37#define INFORM0_OFFSET 0x800
38#define INFORM1_OFFSET 0x804
39#define INFORM2_OFFSET 0x808
40#define INFORM3_OFFSET 0x80c
41
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053042/* select serial console configuration */
43#define CONFIG_BAUDRATE 115200
44#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053045
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053046#define CONFIG_CMD_HASH
47
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053048/* Thermal Management Unit */
49#define CONFIG_EXYNOS_TMU
50#define CONFIG_CMD_DTT
51#define CONFIG_TMU_CMD_DTT
52
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053053/* MMC SPL */
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053054#define COPY_BL2_FNPTR_ADDR 0x02020030
Simon Glass5ea01ab2014-10-07 22:01:45 -060055#define CONFIG_SUPPORT_EMMC_BOOT
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053056
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053057/* specific .lds file */
58#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053059
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053060/* Boot Argument Buffer Size */
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053061/* memtest works on */
62#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
63#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
64#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
65
66#define CONFIG_RD_LVL
67
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053068#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
69#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
70#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
71#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
72#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
73#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
74#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
75#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
76#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
77#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
78#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
79#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
80#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
81#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
82#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
83#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
84
85#define CONFIG_SYS_MONITOR_BASE 0x00000000
86
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +053087#define CONFIG_SYS_MMC_ENV_DEV 0
88
89#define CONFIG_SECURE_BL1_ONLY
90
91/* Secure FW size configuration */
92#ifdef CONFIG_SECURE_BL1_ONLY
93#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
94#else
95#define CONFIG_SEC_FW_SIZE 0
96#endif
97
98/* Configuration of BL1, BL2, ENV Blocks on mmc */
99#define CONFIG_RES_BLOCK_SIZE (512)
100#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
101#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
102#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
103
104#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
105#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
Akshay Saraswatfa253152014-06-18 17:53:59 +0530106
Bin Menga1875592016-02-05 19:30:11 -0800107/* U-Boot copy size from boot Media to DRAM.*/
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530108#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
109#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
110
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530111#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
112#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
113
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530114/* I2C */
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530115#define CONFIG_SYS_I2C_S3C24X0
Przemyslaw Marczak189d8012015-01-27 13:36:39 +0100116#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530117#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530118
119/* SPI */
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530120#ifdef CONFIG_SPI_FLASH
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530121#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
122#define CONFIG_SF_DEFAULT_SPEED 50000000
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530123#endif
124
125#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
126#define CONFIG_ENV_SPI_MODE SPI_MODE_0
127#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
128#define CONFIG_ENV_SPI_BUS 1
129#define CONFIG_ENV_SPI_MAX_HZ 50000000
130#endif
131
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530132/* Ethernet Controllor Driver */
133#ifdef CONFIG_CMD_NET
134#define CONFIG_SMC911X
135#define CONFIG_SMC911X_BASE 0x5000000
136#define CONFIG_SMC911X_16_BIT
137#define CONFIG_ENV_SROM_BANK 1
138#endif /*CONFIG_CMD_NET*/
139
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530140/* SHA hashing */
141#define CONFIG_CMD_HASH
142#define CONFIG_HASH_VERIFY
143#define CONFIG_SHA1
144#define CONFIG_SHA256
145
146/* Enable Time Command */
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530147
Sjoerd Simons66223782014-12-29 22:17:10 +0100148/* USB */
Sjoerd Simons66223782014-12-29 22:17:10 +0100149#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
150#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
151
152#define CONFIG_USB_HOST_ETHER
153#define CONFIG_USB_ETHER_ASIX
154#define CONFIG_USB_ETHER_SMSC95XX
Anand Moon76aab9e2016-03-05 19:38:23 +1030155#define CONFIG_USB_ETHER_RTL8152
Sjoerd Simons66223782014-12-29 22:17:10 +0100156
Akshay Saraswat582693b2014-06-18 17:54:01 +0530157/* USB boot mode */
158#define CONFIG_USB_BOOTING
159#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
160#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
161#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
162
Ian Campbelle6825e02014-11-09 10:44:32 +0000163#define BOOT_TARGET_DEVICES(func) \
164 func(MMC, mmc, 1) \
165 func(MMC, mmc, 0) \
166 func(PXE, pxe, na) \
167 func(DHCP, dhcp, na)
168
169#include <config_distro_bootcmd.h>
170
171#ifndef MEM_LAYOUT_ENV_SETTINGS
172/* 2GB RAM, bootm size of 256M, load scripts after that */
173#define MEM_LAYOUT_ENV_SETTINGS \
174 "bootm_size=0x10000000\0" \
175 "kernel_addr_r=0x42000000\0" \
176 "fdt_addr_r=0x43000000\0" \
177 "ramdisk_addr_r=0x43300000\0" \
178 "scriptaddr=0x50000000\0" \
179 "pxefile_addr_r=0x51000000\0"
180#endif
181
182#ifndef EXYNOS_DEVICE_SETTINGS
183#define EXYNOS_DEVICE_SETTINGS \
184 "stdin=serial\0" \
185 "stdout=serial\0" \
186 "stderr=serial\0"
187#endif
188
189#ifndef EXYNOS_FDTFILE_SETTING
190#define EXYNOS_FDTFILE_SETTING
191#endif
192
193#define CONFIG_EXTRA_ENV_SETTINGS \
194 EXYNOS_DEVICE_SETTINGS \
195 EXYNOS_FDTFILE_SETTING \
196 MEM_LAYOUT_ENV_SETTINGS \
197 BOOTENV
198
Simon Glass4c7bb1d2014-10-07 22:01:44 -0600199#endif /* __CONFIG_EXYNOS5_COMMON_H */