blob: f7352608b55f7e07b7ad0ca1337cf5a7522a1459 [file] [log] [blame]
Marek Vasutd5914012011-01-19 04:40:37 +00001/*
2 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
3 *
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/io.h>
27#include <asm/arch/imx-regs.h>
28#include <asm/arch/mx5x_pins.h>
29#include <asm/arch/iomux.h>
30#include <mxc_gpio.h>
31#include <asm/errno.h>
32#include <asm/arch/sys_proto.h>
33#include <asm/arch/crm_regs.h>
34#include <i2c.h>
35#include <mmc.h>
36#include <fsl_esdhc.h>
37#include <fsl_pmic.h>
38#include <mc13892.h>
39
40DECLARE_GLOBAL_DATA_PTR;
41
42/*
43 * Compile-time error checking
44 */
45#ifndef CONFIG_MXC_SPI
46#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
47#endif
48
49/*
50 * Shared variables / local defines
51 */
52/* LED */
53#define EFIKAMX_LED_BLUE 0x1
54#define EFIKAMX_LED_GREEN 0x2
55#define EFIKAMX_LED_RED 0x4
56
57void efikamx_toggle_led(uint32_t mask);
58
59/* Board revisions */
60#define EFIKAMX_BOARD_REV_11 0x1
61#define EFIKAMX_BOARD_REV_12 0x2
62#define EFIKAMX_BOARD_REV_13 0x3
63#define EFIKAMX_BOARD_REV_14 0x4
64
65/*
66 * Board identification
67 */
68u32 get_efika_rev(void)
69{
70 u32 rev = 0;
71 /*
72 * Retrieve board ID:
73 * rev1.1: 1,1,1
74 * rev1.2: 1,1,0
75 * rev1.3: 1,0,1
76 * rev1.4: 1,0,0
77 */
78 mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
79 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
80 MXC_GPIO_DIRECTION_OUT);
81 /* set to 1 in order to get correct value on board rev1.1 */
82 mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
83
84 mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
85 mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
86 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
87 MXC_GPIO_DIRECTION_IN);
88 rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
89
90 mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
91 mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
92 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1),
93 MXC_GPIO_DIRECTION_IN);
94 rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
95
96 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
97 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
98 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3),
99 MXC_GPIO_DIRECTION_IN);
100 rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
101
102 return (~rev & 0x7) + 1;
103}
104
105u32 get_board_rev(void)
106{
107 return get_cpu_rev() | (get_efika_rev() << 8);
108}
109
110/*
111 * DRAM initialization
112 */
113int dram_init(void)
114{
115 /* dram_init must store complete ramsize in gd->ram_size */
116 gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
117 PHYS_SDRAM_1_SIZE);
118 return 0;
119}
120
121/*
122 * UART configuration
123 */
124static void setup_iomux_uart(void)
125{
126 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
127 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
128
129 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
130 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
131 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
132 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
133 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
134 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
135 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
136 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
137}
138
139/*
140 * SPI configuration
141 */
142#ifdef CONFIG_MXC_SPI
143static void setup_iomux_spi(void)
144{
145 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
146 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
147 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
148 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
149
150 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
151 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
152 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
153 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
154
155 /* Configure SS0 as a GPIO */
156 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
157 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0),
158 MXC_GPIO_DIRECTION_OUT);
159 mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
160
161 /* Configure SS1 as a GPIO */
162 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
163 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1),
164 MXC_GPIO_DIRECTION_OUT);
165 mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
166
167 /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
168 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
169 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
170 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
171
172 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
173 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
174 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
175 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
176}
177#else
178static inline void setup_iomux_spi(void) { }
179#endif
180
181/*
182 * PMIC configuration
183 */
184#ifdef CONFIG_MXC_SPI
185static void power_init(void)
186{
187 unsigned int val;
188 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
189
190 /* Write needed to Power Gate 2 register */
191 val = pmic_reg_read(REG_POWER_MISC);
192 val &= ~PWGT2SPIEN;
193 pmic_reg_write(REG_POWER_MISC, val);
194
195 /* Externally powered */
196 val = pmic_reg_read(REG_CHARGE);
197 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
198 pmic_reg_write(REG_CHARGE, val);
199
200 /* power up the system first */
201 pmic_reg_write(REG_POWER_MISC, PWUP);
202
203 /* Set core voltage to 1.1V */
204 val = pmic_reg_read(REG_SW_0);
205 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
206 pmic_reg_write(REG_SW_0, val);
207
208 /* Setup VCC (SW2) to 1.25 */
209 val = pmic_reg_read(REG_SW_1);
210 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
211 pmic_reg_write(REG_SW_1, val);
212
213 /* Setup 1V2_DIG1 (SW3) to 1.25 */
214 val = pmic_reg_read(REG_SW_2);
215 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
216 pmic_reg_write(REG_SW_2, val);
217 udelay(50);
218
219 /* Raise the core frequency to 800MHz */
220 writel(0x0, &mxc_ccm->cacrr);
221
222 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
223 /* Setup the switcher mode for SW1 & SW2*/
224 val = pmic_reg_read(REG_SW_4);
225 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
226 (SWMODE_MASK << SWMODE2_SHIFT)));
227 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
228 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
229 pmic_reg_write(REG_SW_4, val);
230
231 /* Setup the switcher mode for SW3 & SW4 */
232 val = pmic_reg_read(REG_SW_5);
233 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
234 (SWMODE_MASK << SWMODE4_SHIFT)));
235 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
236 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
237 pmic_reg_write(REG_SW_5, val);
238
239 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
240 val = pmic_reg_read(REG_SETTING_0);
241 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
242 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
243 pmic_reg_write(REG_SETTING_0, val);
244
245 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
246 val = pmic_reg_read(REG_SETTING_1);
247 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
248 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
249 pmic_reg_write(REG_SETTING_1, val);
250
251 /* Configure VGEN3 and VCAM regulators to use external PNP */
252 val = VGEN3CONFIG | VCAMCONFIG;
253 pmic_reg_write(REG_MODE_1, val);
254 udelay(200);
255
256 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
257 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
258 VVIDEOEN | VAUDIOEN | VSDEN;
259 pmic_reg_write(REG_MODE_1, val);
260
261 val = pmic_reg_read(REG_POWER_CTL2);
262 val |= WDIRESET;
263 pmic_reg_write(REG_POWER_CTL2, val);
264
265 udelay(2500);
266}
267#else
268static inline void power_init(void) { }
269#endif
270
271/*
272 * MMC configuration
273 */
274#ifdef CONFIG_FSL_ESDHC
275struct fsl_esdhc_cfg esdhc_cfg[2] = {
276 {MMC_SDHC1_BASE_ADDR, 1},
277 {MMC_SDHC2_BASE_ADDR, 1},
278};
279
280int board_mmc_getcd(u8 *absent, struct mmc *mmc)
281{
282 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
283
284 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
285 *absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
286 else
287 *absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
288
289 return 0;
290}
291int board_mmc_init(bd_t *bis)
292{
293 int ret;
294
295 /* SDHC1 is used on all revisions, setup control pins first */
296 mxc_request_iomux(MX51_PIN_GPIO1_0,
297 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
298 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
299 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
300 PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
301 PAD_CTL_ODE_OPENDRAIN_NONE |
302 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
303 mxc_request_iomux(MX51_PIN_GPIO1_1,
304 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
305 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
306 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
307 PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
308 PAD_CTL_SRE_FAST);
309
310 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0),
311 MXC_GPIO_DIRECTION_IN);
312 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1),
313 MXC_GPIO_DIRECTION_IN);
314
315 /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
316 if (get_efika_rev() < EFIKAMX_BOARD_REV_12) {
317 /* SDHC1 IOMUX */
318 mxc_request_iomux(MX51_PIN_SD1_CMD,
319 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
320 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
321 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
322 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
323
324 mxc_request_iomux(MX51_PIN_SD1_CLK,
325 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
326 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
327 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
328 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
329
330 mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
331 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
332 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
333 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
334
335 mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
336 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
337 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
338 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
339
340 mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
341 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
342 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
343 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
344
345 mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
346 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
347 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
348 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
349
350 /* SDHC2 IOMUX */
351 mxc_request_iomux(MX51_PIN_SD2_CMD,
352 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
353 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
354 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
355
356 mxc_request_iomux(MX51_PIN_SD2_CLK,
357 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
358 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
359 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
360
361 mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
362 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
363 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
364
365 mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
366 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
367 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
368
369 mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
370 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
371 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
372
373 mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
374 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
375 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
376
377 /* SDHC2 Control lines IOMUX */
378 mxc_request_iomux(MX51_PIN_GPIO1_7,
379 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
380 mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
381 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
382 PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
383 PAD_CTL_ODE_OPENDRAIN_NONE |
384 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
385 mxc_request_iomux(MX51_PIN_GPIO1_8,
386 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
387 mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
388 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
389 PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
390 PAD_CTL_SRE_FAST);
391
392 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8),
393 MXC_GPIO_DIRECTION_IN);
394 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7),
395 MXC_GPIO_DIRECTION_IN);
396
397 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
398 if (!ret)
399 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
400 } else { /* New boards use only SDHC1 */
401 /* SDHC1 IOMUX */
402 mxc_request_iomux(MX51_PIN_SD1_CMD,
403 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
404 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
405 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
406
407 mxc_request_iomux(MX51_PIN_SD1_CLK,
408 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
409 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
410 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
411
412 mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
413 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
414 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
415
416 mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
417 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
418 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
419
420 mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
421 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
422 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
423
424 mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
425 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
426 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
427
428 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
429 }
430 return ret;
431}
432#endif
433
434/*
435 * ATA
436 */
437#ifdef CONFIG_MX51_PATA
438#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH)
439void setup_iomux_ata(void)
440{
441 mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
442 mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
443 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
444 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
445 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
446 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
447 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
448 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
449 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
450 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
451 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
452 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
453 mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
454 mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
455 mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
456 mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
457 mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
458 mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
459 mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
460 mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
461 mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
462 mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
463 mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
464 mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
465 mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
466 mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
467 mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
468 mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
469 mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
470 mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
471 mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
472 mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
473 mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
474 mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
475 mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
476 mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
477 mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
478 mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
479 mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
480 mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
481 mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
482 mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
483 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
484 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
485 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
486 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
487 mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
488 mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
489 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
490 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
491 mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
492 mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
493 mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
494 mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
495 mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
496 mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
497 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
498 mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
499}
500#else
501static inline void setup_iomux_ata(void) { }
502#endif
503
504/*
505 * LED configuration
506 */
507void setup_iomux_led(void)
508{
509 /* Blue LED */
510 mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
511 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
512 MXC_GPIO_DIRECTION_OUT);
513 /* Green LED */
514 mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
515 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
516 MXC_GPIO_DIRECTION_OUT);
517 /* Red LED */
518 mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
519 mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
520 MXC_GPIO_DIRECTION_OUT);
521}
522
523void efikamx_toggle_led(uint32_t mask)
524{
525 mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
526 mask & EFIKAMX_LED_BLUE);
527 mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
528 mask & EFIKAMX_LED_GREEN);
529 mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
530 mask & EFIKAMX_LED_RED);
531}
532
533/*
534 * Board initialization
535 */
536static void init_drive_strength(void)
537{
538 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
539 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
540 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
541 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
542 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
543 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
544 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
545 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
546 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
547 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
548 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
549 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
550 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
551 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
552 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
553 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
554 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
555 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
556 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
557 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
558 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
559 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
560 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
561 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
562 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
563 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
564 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
565
566 /* Setting pad options */
567 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
568 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
569 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
570 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
571 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
572 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
573 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
574 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
575 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
576 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
577 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
578 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
579 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
580 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
581 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
582 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
583 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
584 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
585 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
586 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
587 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
588 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
589 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
590 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
591 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
592 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
593 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
594 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
595 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
596 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
597 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
598 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
599 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
600 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
601 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
602 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
603 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
604 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
605 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
606 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
607 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
608 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
609}
610
611int board_early_init_f(void)
612{
613 init_drive_strength();
614
615 setup_iomux_uart();
616 setup_iomux_spi();
617 setup_iomux_led();
618
619 return 0;
620}
621
622int board_init(void)
623{
Loïc Minier0b509512011-02-03 04:19:09 +0000624 gd->bd->bi_arch_number = MACH_TYPE_MX51_EFIKAMX;
Marek Vasutd5914012011-01-19 04:40:37 +0000625 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
626
627 return 0;
628}
629
630int board_late_init(void)
631{
632 setup_iomux_spi();
633
634 power_init();
635
636 setup_iomux_led();
637 setup_iomux_ata();
638
639 efikamx_toggle_led(EFIKAMX_LED_BLUE);
640
641 return 0;
642}
643
644int checkboard(void)
645{
646 u32 system_rev = get_cpu_rev();
647 u32 cause;
648 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
649
650 puts("Board: Efika MX ");
651
652 switch (system_rev & 0xff) {
653 case CHIP_REV_3_0:
654 puts("3.0 [");
655 break;
656 case CHIP_REV_2_5:
657 puts("2.5 [");
658 break;
659 case CHIP_REV_2_0:
660 puts("2.0 [");
661 break;
662 case CHIP_REV_1_1:
663 puts("1.1 [");
664 break;
665 case CHIP_REV_1_0:
666 default:
667 puts("1.0 [");
668 break;
669 }
670
671 cause = src_regs->srsr;
672 switch (cause) {
673 case 0x0001:
674 puts("POR");
675 break;
676 case 0x0009:
677 puts("RST");
678 break;
679 case 0x0010:
680 case 0x0011:
681 puts("WDOG");
682 break;
683 default:
684 printf("unknown 0x%x", cause);
685 }
686 puts("]\n");
687
688 return 0;
689}