blob: e295bac128cb7f1d12963b9b017b041581b66288 [file] [log] [blame]
Michal Simek64eb13b2019-04-12 12:19:22 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "Versal System Controller on a2197 Memory Char board RevA";
Michal Simek50d92832019-06-28 13:16:10 +020017 compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA",
Michal Simek64eb13b2019-04-12 12:19:22 +020018 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
19
20 aliases {
21 ethernet0 = &gem0;
22 gpio0 = &gpio;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci0;
26 mmc1 = &sdhci1;
27 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &dcc;
31 usb0 = &usb0;
32 usb1 = &usb1;
33 spi0 = &qspi;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
39 xlnx,eeprom = <&eeprom>;
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
45 };
Michal Simekeaf96b12019-08-26 11:09:54 +020046
47 ina226-vcc-aux {
48 compatible = "iio-hwmon";
49 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
50 };
51 ina226-vcc-ram {
52 compatible = "iio-hwmon";
53 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
54 };
55 ina226-vcc1v1-lp4 {
56 compatible = "iio-hwmon";
57 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
58 };
59 ina226-vcc1v2-lp4 {
60 compatible = "iio-hwmon";
61 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
62 };
63 ina226-vdd1-1v8-lp4 {
64 compatible = "iio-hwmon";
65 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
66 };
67 ina226-vcc0v6-lp4 {
68 compatible = "iio-hwmon";
69 io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
70 };
Michal Simek64eb13b2019-04-12 12:19:22 +020071};
72
73&qspi {
74 status = "okay";
75 is-dual = <1>;
76 flash@0 {
Michal Simekb954e882019-08-07 09:58:29 +020077 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Michal Simek64eb13b2019-04-12 12:19:22 +020078 #address-cells = <1>;
79 #size-cells = <1>;
80 reg = <0x0>;
81 spi-tx-bus-width = <1>;
82 spi-rx-bus-width = <4>;
83 spi-max-frequency = <108000000>;
84 };
85};
86
87&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
88 status = "okay";
89 non-removable;
90 disable-wp;
91 bus-width = <8>;
92 xlnx,mio_bank = <0>; /* FIXME tap delay */
93};
94
95&uart0 { /* uart0 MIO38-39 */
96 status = "okay";
97 u-boot,dm-pre-reloc;
98};
99
100&uart1 { /* uart1 MIO40-41 */
101 status = "okay";
102 u-boot,dm-pre-reloc;
103};
104
105&sdhci1 { /* sd1 MIO45-51 cd in place */
106 status = "disable";
107 no-1-8-v;
108 disable-wp;
109 xlnx,mio_bank = <1>;
110};
111
112&gem0 {
113 status = "okay";
114 phy-handle = <&phy0>;
115 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
116 phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
Michal Simek2975a422019-08-08 12:44:22 +0200117 phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
Michal Simek64eb13b2019-04-12 12:19:22 +0200118 reg = <0>;
119/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
120 };
121/* phy-names = "...";
122 phys = <&lane0 PHY_TYPE_SGMII ... >
123 Note: lane0 sgmii/lane1 usb3 */
124};
125
126&gpio {
127 status = "okay";
128 gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
129 "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
130 "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
131 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
132 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
133 "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
134 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
135 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
136 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
137 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
138 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
139 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
140 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
141 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
142 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
143 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
144 "", "", "", "", "", /* 78 - 79 */
145 "", "", "", "", "", /* 80 - 84 */
146 "", "", "", "", "", /* 85 -89 */
147 "", "", "", "", "", /* 90 - 94 */
148 "", "", "", "", "", /* 95 - 99 */
149 "", "", "", "", "", /* 100 - 104 */
150 "", "", "", "", "", /* 105 - 109 */
151 "", "", "", "", "", /* 110 - 114 */
152 "", "", "", "", "", /* 115 - 119 */
153 "", "", "", "", "", /* 120 - 124 */
154 "", "", "", "", "", /* 125 - 129 */
155 "", "", "", "", "", /* 130 - 134 */
156 "", "", "", "", "", /* 135 - 139 */
157 "", "", "", "", "", /* 140 - 144 */
158 "", "", "", "", "", /* 145 - 149 */
159 "", "", "", "", "", /* 150 - 154 */
160 "", "", "", "", "", /* 155 - 159 */
161 "", "", "", "", "", /* 160 - 164 */
162 "", "", "", "", "", /* 165 - 169 */
163 "", "", "", ""; /* 170 - 174 */
164};
165
166&i2c0 { /* MIO 34-35 - can't stay here */
167 status = "okay";
168 clock-frequency = <400000>;
169 i2c-mux@74 { /* u46 */
170 compatible = "nxp,pca9548";
171 #address-cells = <1>;
172 #size-cells = <0>;
173 reg = <0x74>;
174 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
175 i2c@0 { /* PMBUS must be enabled via SW21 */
176 #address-cells = <1>;
177 #size-cells = <0>;
178 reg = <0>;
179 reg_vcc1v2_lp4: tps544@15 { /* u97 */
180 compatible = "ti,tps544b25";
181 reg = <0x15>;
182 };
183 reg_vcc1v1_lp4: tps544@16 { /* u95 */
184 compatible = "ti,tps544b25";
185 reg = <0x16>;
186 };
187 reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
188 compatible = "ti,tps544b25";
189 reg = <0x17>;
190 };
191 /* UTIL_PMBUS connection */
192 reg_vcc1v8: tps544@13 { /* u92 */
193 compatible = "ti,tps544b25";
194 reg = <0x13>;
195 };
196 reg_vcc3v3: tps544@14 { /* u93 */
197 compatible = "ti,tps544b25";
198 reg = <0x14>;
199 };
200 reg_vcc5v0: tps544@1e { /* u94 */
201 compatible = "ti,tps544b25";
202 reg = <0x1e>;
203 };
204 };
205 i2c@1 { /* PMBUS_INA226 */
206 #address-cells = <1>;
207 #size-cells = <0>;
208 reg = <1>;
209 vcc_aux: ina226@42 { /* u86 */
210 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200211 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200212 label = "ina226-vcc-aux";
Michal Simek64eb13b2019-04-12 12:19:22 +0200213 reg = <0x42>;
214 shunt-resistor = <5000>;
215 };
216 vcc_ram: ina226@43 { /* u81 */
217 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200218 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200219 label = "ina226-vcc-ram";
Michal Simek64eb13b2019-04-12 12:19:22 +0200220 reg = <0x43>;
221 shunt-resistor = <5000>;
222 };
223 vcc1v1_lp4: ina226@46 { /* u96 */
224 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200225 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200226 label = "ina226-vcc1v1-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200227 reg = <0x46>;
228 shunt-resistor = <5000>;
229 };
230 vcc1v2_lp4: ina226@47 { /* u98 */
231 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200232 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200233 label = "ina226-vcc1v2-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200234 reg = <0x47>;
235 shunt-resistor = <5000>;
236 };
237 vdd1_1v8_lp4: ina226@48 { /* u100 */
238 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200239 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200240 label = "ina226-vdd1-1v8-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200241 reg = <0x48>;
242 shunt-resistor = <5000>;
243 };
244 vcc0v6_lp4: ina226@49 { /* u101 */
245 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200246 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200247 label = "ina226-vcc0v6-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200248 reg = <0x49>;
249 shunt-resistor = <5000>;
250 };
251 };
252 i2c@2 { /* PMBUS1 */
253 #address-cells = <1>;
254 #size-cells = <0>;
255 reg = <2>;
256 reg_vccint: tps53681@c0 { /* u69 */
Nishant Mittalebb28f22019-07-24 14:58:52 +0530257 compatible = "ti,tps53681", "ti,tps53679";
Michal Simek64eb13b2019-04-12 12:19:22 +0200258 reg = <0xc0>;
259 };
260 reg_vcc_pmc: tps544@7 { /* u80 */
261 compatible = "ti,tps544b25";
262 reg = <0x7>;
263 };
264 reg_vcc_ram: tps544@8 { /* u82 */
265 compatible = "ti,tps544b25";
266 reg = <0x8>;
267 };
268 reg_vcc_pslp: tps544@9 { /* u83 */
269 compatible = "ti,tps544b25";
270 reg = <0x9>;
271 };
272 reg_vcc_psfp: tps544@a { /* u84 */
273 compatible = "ti,tps544b25";
274 reg = <0xa>;
275 };
276 reg_vccaux: tps544@d { /* u85 */
277 compatible = "ti,tps544b25";
278 reg = <0xd>;
279 };
280 reg_vccaux_pmc: tps544@e { /* u87 */
281 compatible = "ti,tps544b25";
282 reg = <0xe>;
283 };
284 reg_vcco_500: tps544@f { /* u88 */
285 compatible = "ti,tps544b25";
286 reg = <0xf>;
287 };
288 reg_vcco_501: tps544@10 { /* u89 */
289 compatible = "ti,tps544b25";
290 reg = <0x10>;
291 };
292 reg_vcco_502: tps544@11 { /* u90 */
293 compatible = "ti,tps544b25";
294 reg = <0x11>;
295 };
296 reg_vcco_503: tps544@12 { /* u91 */
297 compatible = "ti,tps544b25";
298 reg = <0x12>;
299 };
300 };
301 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
302 #address-cells = <1>;
303 #size-cells = <0>;
304 /* reg = <3>; */
305 };
306 i2c@4 { /* LP_I2C_SM */
307 #address-cells = <1>;
308 #size-cells = <0>;
309 reg = <4>;
310 /* connected to U20G */
311 };
312 /* 5-7 unused */
313 };
314};
315
316/* TODO sysctrl via J239 */
317/* TODO samtec J212G/H via J242 */
318/* TODO teensy via U30 PCA9543A bus 1 */
319&i2c1 { /* i2c1 MIO 36-37 */
320 status = "okay";
321 clock-frequency = <400000>;
322
323 /* Must be enabled via J242 */
324 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
325 compatible = "atmel,24c02";
326 reg = <0x51>;
327 };
328
Michal Simek2703d4b2019-06-28 13:52:09 +0200329 i2c-mux@74 { /* u47 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200330 compatible = "nxp,pca9548";
331 #address-cells = <1>;
332 #size-cells = <0>;
333 reg = <0x74>;
334 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
335 dc_i2c: i2c@0 { /* DC_I2C */
336 #address-cells = <1>;
337 #size-cells = <0>;
338 reg = <0>;
339 /* Use for storing information about SC board */
340 eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
341 compatible = "atmel,24c08";
342 reg = <0x54>;
343 };
344 si570_ref_clk: clock-generator@5d { /* u26 */
345 #clock-cells = <0>;
346 compatible = "silabs,si570";
347 reg = <0x5d>; /* FIXME addr */
348 temperature-stability = <50>;
349 factory-fout = <156250000>; /* FIXME every chip can be different */
350 clock-frequency = <33333333>;
351 clock-output-names = "REF_CLK"; /* FIXME */
352 };
353 /* Connection via Samtec U20D */
354 /* Use for storing information about X-PRC card */
355 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
356 compatible = "atmel,24c02";
357 reg = <0x52>;
358 };
359
360 /* Use for setting up certain features on X-PRC card */
361 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
362 compatible = "nxp,pca9534";
363 reg = <0x22>;
364 gpio-controller; /* IRQ not connected */
365 #gpio-cells = <2>;
366 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
367 "", "", "", "";
368 gtr_sel0 {
369 gpio-hog;
370 gpios = <0 0>;
371 input; /* FIXME add meaning */
372 line-name = "sw4_1";
373 };
374 gtr_sel1 {
375 gpio-hog;
376 gpios = <1 0>;
377 input; /* FIXME add meaning */
378 line-name = "sw4_2";
379 };
380 gtr_sel2 {
381 gpio-hog;
382 gpios = <2 0>;
383 input; /* FIXME add meaning */
384 line-name = "sw4_3";
385 };
386 gtr_sel3 {
387 gpio-hog;
388 gpios = <3 0>;
389 input; /* FIXME add meaning */
390 line-name = "sw4_4";
391 };
392 };
393 };
Michal Simek64eb13b2019-04-12 12:19:22 +0200394 i2c@2 { /* C0_LP4 */
395 #address-cells = <1>;
396 #size-cells = <0>;
397 reg = <2>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200398 si570_c0_lp4: clock-generator@55 { /* u10 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200399 #clock-cells = <0>;
400 compatible = "silabs,si570";
Michal Simek2703d4b2019-06-28 13:52:09 +0200401 reg = <0x55>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200402 temperature-stability = <50>;
403 factory-fout = <30000000>;
404 clock-frequency = <30000000>;
405 clock-output-names = "C0_LP4_SI570_CLK";
406 };
407 };
408 i2c@3 { /* C1_LP4 */
409 #address-cells = <1>;
410 #size-cells = <0>;
411 reg = <3>;
412 si570_c1_lp4: clock-generator@5d { /* u10 */
413 #clock-cells = <0>;
414 compatible = "silabs,si570";
415 reg = <0x5d>; /* FIXME addr */
416 temperature-stability = <50>;
417 factory-fout = <30000000>;
418 clock-frequency = <30000000>;
419 clock-output-names = "C1_LP4_SI570_CLK";
420 };
421 };
422 i2c@4 { /* C2_LP4 */
423 #address-cells = <1>;
424 #size-cells = <0>;
425 reg = <4>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200426 si570_c2_lp4: clock-generator@55 { /* u10 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200427 #clock-cells = <0>;
428 compatible = "silabs,si570";
Michal Simek2703d4b2019-06-28 13:52:09 +0200429 reg = <0x55>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200430 temperature-stability = <50>;
431 factory-fout = <30000000>;
432 clock-frequency = <30000000>;
433 clock-output-names = "C2_LP4_SI570_CLK";
434 };
435 };
436 i2c@5 { /* C3_LP4 */
437 #address-cells = <1>;
438 #size-cells = <0>;
439 reg = <5>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200440 si570_c3_lp4: clock-generator@55 { /* u15 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200441 #clock-cells = <0>;
442 compatible = "silabs,si570";
Michal Simek2703d4b2019-06-28 13:52:09 +0200443 reg = <0x55>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200444 temperature-stability = <50>;
445 factory-fout = <30000000>;
446 clock-frequency = <30000000>;
447 clock-output-names = "C3_LP4_SI570_CLK";
448 };
449 };
450 i2c@6 { /* HSDP_SI570 */
451 #address-cells = <1>;
452 #size-cells = <0>;
453 reg = <6>;
454 si570_hsdp: clock-generator@5d { /* u19 */
455 #clock-cells = <0>;
456 compatible = "silabs,si570";
457 reg = <0x5d>; /* FIXME addr */
458 temperature-stability = <50>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200459 factory-fout = <156250000>;
460 clock-frequency = <156250000>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200461 clock-output-names = "HSDP_SI570";
462 };
463 };
464 };
465};
466
467&usb0 {
468 status = "okay";
469 xlnx,usb-polarity = <0>;
470 xlnx,usb-reset-mode = <0>;
471};
472
473&dwc3_0 {
474 status = "okay";
475 dr_mode = "host";
476 /* dr_mode = "peripheral"; */
477 maximum-speed = "high-speed";
478};
479
480&usb1 {
481 status = "disabled"; /* not at mem board */
482 xlnx,usb-polarity = <0>;
483 xlnx,usb-reset-mode = <0>;
484};
485
486&dwc3_1 {
487 /delete-property/ phy-names ;
488 /delete-property/ phys ;
489 maximum-speed = "high-speed";
490 snps,dis_u2_susphy_quirk ;
491 snps,dis_u3_susphy_quirk ;
492 status = "disabled";
493};