blob: 5c76fd962e98e5386418fe29e84cdc60f69221f2 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Mingkai Hu273feaf2011-04-26 16:31:16 +08002/*
3 * eSPI controller driver.
4 *
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Chuanhua Han8d505512020-06-04 23:16:30 +08006 * Copyright 2020 NXP
Mingkai Hu273feaf2011-04-26 16:31:16 +08007 * Author: Mingkai Hu (Mingkai.hu@freescale.com)
Chuanhua Han8d505512020-06-04 23:16:30 +08008 * Chuanhua Han (chuanhua.han@nxp.com)
Mingkai Hu273feaf2011-04-26 16:31:16 +08009 */
10
11#include <common.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Simon Glasscd93d622020-05-10 11:40:13 -060013#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060014#include <linux/delay.h>
Mingkai Hu273feaf2011-04-26 16:31:16 +080015
16#include <malloc.h>
17#include <spi.h>
18#include <asm/immap_85xx.h>
Chuanhua Han8d505512020-06-04 23:16:30 +080019#include <dm.h>
20#include <errno.h>
21#include <fdtdec.h>
22#include <dm/platform_data/fsl_espi.h>
Mingkai Hu273feaf2011-04-26 16:31:16 +080023
24struct fsl_spi_slave {
25 struct spi_slave slave;
Hou Zhiqiangafb90702014-05-21 10:25:10 +080026 ccsr_espi_t *espi;
Chuanhua Han8d505512020-06-04 23:16:30 +080027 u32 speed_hz;
28 unsigned int cs;
Mingkai Hu273feaf2011-04-26 16:31:16 +080029 unsigned int div16;
30 unsigned int pm;
Hou Zhiqiangafb90702014-05-21 10:25:10 +080031 int tx_timeout;
Mingkai Hu273feaf2011-04-26 16:31:16 +080032 unsigned int mode;
33 size_t cmd_len;
34 u8 cmd_buf[16];
35 size_t data_len;
36 unsigned int max_transfer_length;
37};
38
39#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
Hou Zhiqiangafb90702014-05-21 10:25:10 +080040#define US_PER_SECOND 1000000UL
Mingkai Hu273feaf2011-04-26 16:31:16 +080041
Chuanhua Han8d505512020-06-04 23:16:30 +080042/* default SCK frequency, unit: HZ */
43#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000
44
Mingkai Hu273feaf2011-04-26 16:31:16 +080045#define ESPI_MAX_CS_NUM 4
Hou Zhiqiangafb90702014-05-21 10:25:10 +080046#define ESPI_FIFO_WIDTH_BIT 32
Mingkai Hu273feaf2011-04-26 16:31:16 +080047
Jagan Teki29e6abd2015-10-23 01:37:18 +053048#define ESPI_EV_RNE BIT(9)
49#define ESPI_EV_TNF BIT(8)
50#define ESPI_EV_DON BIT(14)
51#define ESPI_EV_TXE BIT(15)
Hou Zhiqiangafb90702014-05-21 10:25:10 +080052#define ESPI_EV_RFCNT_SHIFT 24
53#define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT)
Mingkai Hu273feaf2011-04-26 16:31:16 +080054
Jagan Teki29e6abd2015-10-23 01:37:18 +053055#define ESPI_MODE_EN BIT(31) /* Enable interface */
Mingkai Hu273feaf2011-04-26 16:31:16 +080056#define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */
57#define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */
58
59#define ESPI_COM_CS(x) ((x) << 30)
60#define ESPI_COM_TRANLEN(x) ((x) << 0)
61
Jagan Teki29e6abd2015-10-23 01:37:18 +053062#define ESPI_CSMODE_CI_INACTIVEHIGH BIT(31)
63#define ESPI_CSMODE_CP_BEGIN_EDGCLK BIT(30)
64#define ESPI_CSMODE_REV_MSB_FIRST BIT(29)
65#define ESPI_CSMODE_DIV16 BIT(28)
Mingkai Hu273feaf2011-04-26 16:31:16 +080066#define ESPI_CSMODE_PM(x) ((x) << 24)
Jagan Teki29e6abd2015-10-23 01:37:18 +053067#define ESPI_CSMODE_POL_ASSERTED_LOW BIT(20)
Mingkai Hu273feaf2011-04-26 16:31:16 +080068#define ESPI_CSMODE_LEN(x) ((x) << 16)
69#define ESPI_CSMODE_CSBEF(x) ((x) << 12)
70#define ESPI_CSMODE_CSAFT(x) ((x) << 8)
71#define ESPI_CSMODE_CSCG(x) ((x) << 3)
72
73#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \
74 ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
75 ESPI_CSMODE_CSCG(1))
76
77#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
78
Chuanhua Han8d505512020-06-04 23:16:30 +080079void fsl_spi_cs_activate(struct spi_slave *slave, uint cs)
Mingkai Hu273feaf2011-04-26 16:31:16 +080080{
81 struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
Hou Zhiqiangafb90702014-05-21 10:25:10 +080082 ccsr_espi_t *espi = fsl->espi;
Chuanhua Han8d505512020-06-04 23:16:30 +080083 unsigned int com = 0;
84 size_t data_len = fsl->data_len;
Mingkai Hu273feaf2011-04-26 16:31:16 +080085
Chuanhua Han8d505512020-06-04 23:16:30 +080086 com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
87 com |= ESPI_COM_CS(cs);
88 com |= ESPI_COM_TRANLEN(data_len - 1);
89 out_be32(&espi->com, com);
Mingkai Hu273feaf2011-04-26 16:31:16 +080090}
91
Chuanhua Han8d505512020-06-04 23:16:30 +080092void fsl_spi_cs_deactivate(struct spi_slave *slave)
Mingkai Hu273feaf2011-04-26 16:31:16 +080093{
Chuanhua Han8d505512020-06-04 23:16:30 +080094 struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
95 ccsr_espi_t *espi = fsl->espi;
Mingkai Hu273feaf2011-04-26 16:31:16 +080096
Chuanhua Han8d505512020-06-04 23:16:30 +080097 /* clear the RXCNT and TXCNT */
98 out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
99 out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800100}
101
Hou Zhiqiangafb90702014-05-21 10:25:10 +0800102static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
103{
104 ccsr_espi_t *espi = fsl->espi;
105 unsigned int tmpdout, event;
106 int tmp_tx_timeout;
107
108 if (dout)
109 tmpdout = *(u32 *)dout;
110 else
111 tmpdout = 0;
112
113 out_be32(&espi->tx, tmpdout);
114 out_be32(&espi->event, ESPI_EV_TNF);
115 debug("***spi_xfer:...%08x written\n", tmpdout);
116
117 tmp_tx_timeout = fsl->tx_timeout;
118 /* Wait for eSPI transmit to go out */
119 while (tmp_tx_timeout--) {
120 event = in_be32(&espi->event);
121 if (event & ESPI_EV_DON || event & ESPI_EV_TXE) {
122 out_be32(&espi->event, ESPI_EV_TXE);
123 break;
124 }
125 udelay(1);
126 }
127
128 if (tmp_tx_timeout < 0)
129 debug("***spi_xfer:...Tx timeout! event = %08x\n", event);
130}
131
Chuanhua Han8d505512020-06-04 23:16:30 +0800132static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
133 unsigned int bytes)
Hou Zhiqiangafb90702014-05-21 10:25:10 +0800134{
135 ccsr_espi_t *espi = fsl->espi;
136 unsigned int tmpdin, rx_times;
137 unsigned char *buf, *p_cursor;
138
139 if (bytes <= 0)
140 return 0;
141
142 rx_times = DIV_ROUND_UP(bytes, 4);
143 buf = (unsigned char *)malloc(4 * rx_times);
144 if (!buf) {
145 debug("SF: Failed to malloc memory.\n");
146 return -1;
147 }
148 p_cursor = buf;
149 while (rx_times--) {
150 tmpdin = in_be32(&espi->rx);
151 debug("***spi_xfer:...%08x readed\n", tmpdin);
152 *(u32 *)p_cursor = tmpdin;
153 p_cursor += 4;
154 }
155
156 if (din)
157 memcpy(din, buf, bytes);
158
159 free(buf);
160 out_be32(&espi->event, ESPI_EV_RNE);
161
162 return bytes;
163}
164
Chuanhua Han8d505512020-06-04 23:16:30 +0800165void espi_release_bus(struct fsl_spi_slave *fsl)
Mingkai Hu273feaf2011-04-26 16:31:16 +0800166{
Chuanhua Han8d505512020-06-04 23:16:30 +0800167 /* Disable the SPI hardware */
168 out_be32(&fsl->espi->mode,
169 in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN));
170}
171
172int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen,
173 const void *data_out, void *data_in, unsigned long flags)
174{
175 struct spi_slave *slave = &fsl->slave;
Hou Zhiqiangafb90702014-05-21 10:25:10 +0800176 ccsr_espi_t *espi = fsl->espi;
177 unsigned int event, rx_bytes;
Mingkai Hu273feaf2011-04-26 16:31:16 +0800178 const void *dout = NULL;
179 void *din = NULL;
180 int len = 0;
181 int num_blks, num_chunks, max_tran_len, tran_len;
182 int num_bytes;
Mingkai Hu273feaf2011-04-26 16:31:16 +0800183 unsigned char *buffer = NULL;
184 size_t buf_len;
185 u8 *cmd_buf = fsl->cmd_buf;
186 size_t cmd_len = fsl->cmd_len;
187 size_t data_len = bitlen / 8;
188 size_t rx_offset = 0;
Hou Zhiqiangafb90702014-05-21 10:25:10 +0800189 int rf_cnt;
Mingkai Hu273feaf2011-04-26 16:31:16 +0800190
191 max_tran_len = fsl->max_transfer_length;
192 switch (flags) {
193 case SPI_XFER_BEGIN:
Chuanhua Han8d505512020-06-04 23:16:30 +0800194 cmd_len = data_len;
195 fsl->cmd_len = cmd_len;
Mingkai Hu273feaf2011-04-26 16:31:16 +0800196 memcpy(cmd_buf, data_out, cmd_len);
197 return 0;
198 case 0:
199 case SPI_XFER_END:
200 if (bitlen == 0) {
Chuanhua Han8d505512020-06-04 23:16:30 +0800201 fsl_spi_cs_deactivate(slave);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800202 return 0;
203 }
Masahiro Yamadab4141192014-11-07 03:03:31 +0900204 buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800205 len = cmd_len + data_len;
206 rx_offset = cmd_len;
207 buffer = (unsigned char *)malloc(buf_len);
208 if (!buffer) {
209 debug("SF: Failed to malloc memory.\n");
210 return 1;
211 }
212 memcpy(buffer, cmd_buf, cmd_len);
Shaohui Xie99057572012-10-11 20:31:46 +0000213 if (data_in == NULL)
214 memcpy(buffer + cmd_len, data_out, data_len);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800215 break;
216 case SPI_XFER_BEGIN | SPI_XFER_END:
217 len = data_len;
218 buffer = (unsigned char *)malloc(len * 2);
219 if (!buffer) {
220 debug("SF: Failed to malloc memory.\n");
221 return 1;
222 }
223 memcpy(buffer, data_out, len);
224 rx_offset = len;
225 cmd_len = 0;
226 break;
227 }
228
Hou Zhiqiangafb90702014-05-21 10:25:10 +0800229 debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) len %u\n",
230 *(uint *)data_out, data_out, *(uint *)data_in, data_in, len);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800231
Axel Lina444aa72013-07-12 17:41:08 +0800232 num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800233 while (num_chunks--) {
234 if (data_in)
235 din = buffer + rx_offset;
236 dout = buffer;
Masahiro Yamadab4141192014-11-07 03:03:31 +0900237 tran_len = min(data_len, (size_t)max_tran_len);
Axel Lina444aa72013-07-12 17:41:08 +0800238 num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800239 num_bytes = (tran_len + cmd_len) % 4;
240 fsl->data_len = tran_len + cmd_len;
Chuanhua Han8d505512020-06-04 23:16:30 +0800241 fsl_spi_cs_activate(slave, cs);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800242
243 /* Clear all eSPI events */
244 out_be32(&espi->event , 0xffffffff);
245 /* handle data in 32-bit chunks */
Hou Zhiqiangafb90702014-05-21 10:25:10 +0800246 while (num_blks) {
Mingkai Hu273feaf2011-04-26 16:31:16 +0800247 event = in_be32(&espi->event);
248 if (event & ESPI_EV_TNF) {
Hou Zhiqiangafb90702014-05-21 10:25:10 +0800249 fsl_espi_tx(fsl, dout);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800250 /* Set up the next iteration */
251 if (len > 4) {
252 len -= 4;
253 dout += 4;
254 }
Mingkai Hu273feaf2011-04-26 16:31:16 +0800255 }
256
Mingkai Hu273feaf2011-04-26 16:31:16 +0800257 event = in_be32(&espi->event);
258 if (event & ESPI_EV_RNE) {
Hou Zhiqiangafb90702014-05-21 10:25:10 +0800259 rf_cnt = ((event & ESPI_EV_RFCNT_MASK)
260 >> ESPI_EV_RFCNT_SHIFT);
261 if (rf_cnt >= 4)
262 rx_bytes = 4;
263 else if (num_blks == 1 && rf_cnt == num_bytes)
264 rx_bytes = num_bytes;
265 else
266 continue;
267 if (fsl_espi_rx(fsl, din, rx_bytes)
268 == rx_bytes) {
269 num_blks--;
270 if (din)
271 din = (unsigned char *)din
272 + rx_bytes;
Mingkai Hu273feaf2011-04-26 16:31:16 +0800273 }
Mingkai Hu273feaf2011-04-26 16:31:16 +0800274 }
275 }
276 if (data_in) {
277 memcpy(data_in, buffer + 2 * cmd_len, tran_len);
278 if (*buffer == 0x0b) {
279 data_in += tran_len;
280 data_len -= tran_len;
281 *(int *)buffer += tran_len;
282 }
283 }
Chuanhua Han8d505512020-06-04 23:16:30 +0800284 fsl_spi_cs_deactivate(slave);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800285 }
286
287 free(buffer);
288 return 0;
289}
290
Chuanhua Han8d505512020-06-04 23:16:30 +0800291void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs)
292{
293 ccsr_espi_t *espi = fsl->espi;
294 unsigned char pm = fsl->pm;
295 unsigned int mode = fsl->mode;
296 unsigned int div16 = fsl->div16;
297 int i;
298
299 /* Enable eSPI interface */
300 out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
301 | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
302
303 out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
304 out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */
305
306 /* Init CS mode interface */
307 for (i = 0; i < ESPI_MAX_CS_NUM; i++)
308 out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
309
310 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
311 ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
312 | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
313 | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
314
315 /* Set eSPI BRG clock source */
316 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
317 | ESPI_CSMODE_PM(pm) | div16);
318
319 /* Set eSPI mode */
320 if (mode & SPI_CPHA)
321 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
322 | ESPI_CSMODE_CP_BEGIN_EDGCLK);
323 if (mode & SPI_CPOL)
324 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
325 | ESPI_CSMODE_CI_INACTIVEHIGH);
326
327 /* Character bit order: msb first */
328 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
329 | ESPI_CSMODE_REV_MSB_FIRST);
330
331 /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
332 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
333 | ESPI_CSMODE_LEN(7));
334}
335
336void espi_setup_slave(struct fsl_spi_slave *fsl)
337{
338 unsigned int max_hz;
339 sys_info_t sysinfo;
340 unsigned long spibrg = 0;
341 unsigned long spi_freq = 0;
342 unsigned char pm = 0;
343
344 max_hz = fsl->speed_hz;
345
346 get_sys_info(&sysinfo);
347 spibrg = sysinfo.freq_systembus / 2;
348 fsl->div16 = 0;
349 if ((spibrg / max_hz) > 32) {
350 fsl->div16 = ESPI_CSMODE_DIV16;
351 pm = spibrg / (max_hz * 16 * 2);
352 if (pm > 16) {
353 pm = 16;
354 debug("max_hz is too low: %d Hz, %ld Hz is used.\n",
355 max_hz, spibrg / (32 * 16));
356 }
357 } else {
358 pm = spibrg / (max_hz * 2);
359 }
360 if (pm)
361 pm--;
362 fsl->pm = pm;
363
364 if (fsl->div16)
365 spi_freq = spibrg / ((pm + 1) * 2 * 16);
366 else
367 spi_freq = spibrg / ((pm + 1) * 2);
368
369 /* set tx_timeout to 10 times of one espi FIFO entry go out */
370 fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
371 * 10), spi_freq);/* Set eSPI BRG clock source */
372}
373
374#if !CONFIG_IS_ENABLED(DM_SPI)
Mingkai Hu273feaf2011-04-26 16:31:16 +0800375int spi_cs_is_valid(unsigned int bus, unsigned int cs)
376{
377 return bus == 0 && cs < ESPI_MAX_CS_NUM;
378}
379
Chuanhua Han8d505512020-06-04 23:16:30 +0800380struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
381 unsigned int max_hz, unsigned int mode)
Mingkai Hu273feaf2011-04-26 16:31:16 +0800382{
Chuanhua Han8d505512020-06-04 23:16:30 +0800383 struct fsl_spi_slave *fsl;
Mingkai Hu273feaf2011-04-26 16:31:16 +0800384
Chuanhua Han8d505512020-06-04 23:16:30 +0800385 if (!spi_cs_is_valid(bus, cs))
386 return NULL;
387
388 fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
389 if (!fsl)
390 return NULL;
391
392 fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
393 fsl->mode = mode;
394 fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
395 fsl->speed_hz = max_hz;
396
397 espi_setup_slave(fsl);
398
399 return &fsl->slave;
Mingkai Hu273feaf2011-04-26 16:31:16 +0800400}
401
Chuanhua Han8d505512020-06-04 23:16:30 +0800402void spi_free_slave(struct spi_slave *slave)
Mingkai Hu273feaf2011-04-26 16:31:16 +0800403{
Hou Zhiqiangafb90702014-05-21 10:25:10 +0800404 struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800405
Chuanhua Han8d505512020-06-04 23:16:30 +0800406 free(fsl);
Mingkai Hu273feaf2011-04-26 16:31:16 +0800407}
Chuanhua Han8d505512020-06-04 23:16:30 +0800408
409int spi_claim_bus(struct spi_slave *slave)
410{
411 struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
412
413 espi_claim_bus(fsl, slave->cs);
414
415 return 0;
416}
417
418void spi_release_bus(struct spi_slave *slave)
419{
420 struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
421
422 espi_release_bus(fsl);
423}
424
425int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
426 void *din, unsigned long flags)
427{
428 struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;
429
430 return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags);
431}
432#else
433static void __espi_set_speed(struct fsl_spi_slave *fsl)
434{
435 espi_setup_slave(fsl);
436
437 /* Set eSPI BRG clock source */
438 out_be32(&fsl->espi->csmode[fsl->cs],
439 in_be32(&fsl->espi->csmode[fsl->cs])
440 | ESPI_CSMODE_PM(fsl->pm) | fsl->div16);
441}
442
443static void __espi_set_mode(struct fsl_spi_slave *fsl)
444{
445 /* Set eSPI mode */
446 if (fsl->mode & SPI_CPHA)
447 out_be32(&fsl->espi->csmode[fsl->cs],
448 in_be32(&fsl->espi->csmode[fsl->cs])
449 | ESPI_CSMODE_CP_BEGIN_EDGCLK);
450 if (fsl->mode & SPI_CPOL)
451 out_be32(&fsl->espi->csmode[fsl->cs],
452 in_be32(&fsl->espi->csmode[fsl->cs])
453 | ESPI_CSMODE_CI_INACTIVEHIGH);
454}
455
456static int fsl_espi_claim_bus(struct udevice *dev)
457{
458 struct udevice *bus = dev->parent;
459 struct fsl_spi_slave *fsl = dev_get_priv(bus);
460
461 espi_claim_bus(fsl, fsl->cs);
462
463 return 0;
464}
465
466static int fsl_espi_release_bus(struct udevice *dev)
467{
468 struct udevice *bus = dev->parent;
469 struct fsl_spi_slave *fsl = dev_get_priv(bus);
470
471 espi_release_bus(fsl);
472
473 return 0;
474}
475
476static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
477 const void *dout, void *din, unsigned long flags)
478{
479 struct udevice *bus = dev->parent;
480 struct fsl_spi_slave *fsl = dev_get_priv(bus);
481
482 return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags);
483}
484
485static int fsl_espi_set_speed(struct udevice *bus, uint speed)
486{
487 struct fsl_spi_slave *fsl = dev_get_priv(bus);
488
489 debug("%s speed %u\n", __func__, speed);
490 fsl->speed_hz = speed;
491
492 __espi_set_speed(fsl);
493
494 return 0;
495}
496
497static int fsl_espi_set_mode(struct udevice *bus, uint mode)
498{
499 struct fsl_spi_slave *fsl = dev_get_priv(bus);
500
501 debug("%s mode %u\n", __func__, mode);
502 fsl->mode = mode;
503
504 __espi_set_mode(fsl);
505
506 return 0;
507}
508
509static int fsl_espi_child_pre_probe(struct udevice *dev)
510{
511 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
512 struct udevice *bus = dev->parent;
513 struct fsl_spi_slave *fsl = dev_get_priv(bus);
514
515 debug("%s cs %u\n", __func__, slave_plat->cs);
516 fsl->cs = slave_plat->cs;
517
518 return 0;
519}
520
521static int fsl_espi_probe(struct udevice *bus)
522{
523 struct fsl_espi_platdata *plat = dev_get_platdata(bus);
524 struct fsl_spi_slave *fsl = dev_get_priv(bus);
525
526 fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
527 fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
528 fsl->speed_hz = plat->speed_hz;
529
530 debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
531
532 return 0;
533}
534
535static const struct dm_spi_ops fsl_espi_ops = {
536 .claim_bus = fsl_espi_claim_bus,
537 .release_bus = fsl_espi_release_bus,
538 .xfer = fsl_espi_xfer,
539 .set_speed = fsl_espi_set_speed,
540 .set_mode = fsl_espi_set_mode,
541};
542
543#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
544static int fsl_espi_ofdata_to_platdata(struct udevice *bus)
545{
546 fdt_addr_t addr;
547 struct fsl_espi_platdata *plat = bus->platdata;
548 const void *blob = gd->fdt_blob;
549 int node = dev_of_offset(bus);
550
551 addr = dev_read_addr(bus);
552 if (addr == FDT_ADDR_T_NONE)
553 return -EINVAL;
554
555 plat->regs_addr = lower_32_bits(addr);
556 plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
557 FSL_ESPI_DEFAULT_SCK_FREQ);
558
559 debug("ESPI: regs=%p, max-frequency=%d\n",
560 &plat->regs_addr, plat->speed_hz);
561
562 return 0;
563}
564
565static const struct udevice_id fsl_espi_ids[] = {
566 { .compatible = "fsl,mpc8536-espi" },
567 { }
568};
569#endif
570
571U_BOOT_DRIVER(fsl_espi) = {
572 .name = "fsl_espi",
573 .id = UCLASS_SPI,
574#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
575 .of_match = fsl_espi_ids,
576 .ofdata_to_platdata = fsl_espi_ofdata_to_platdata,
577#endif
578 .ops = &fsl_espi_ops,
579 .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),
580 .priv_auto_alloc_size = sizeof(struct fsl_spi_slave),
581 .probe = fsl_espi_probe,
582 .child_pre_probe = fsl_espi_child_pre_probe,
583};
584#endif