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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chris Zankel7e270ec2016-08-10 18:36:48 +03002/*
3 * (C) Copyright 2007 - 2013 Tensilica Inc.
4 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
Chris Zankel7e270ec2016-08-10 18:36:48 +03005 */
6
7#include <common.h>
Tom Rini2f8a6db2021-12-14 13:36:40 -05008#include <clock_legacy.h>
Chris Zankel7e270ec2016-08-10 18:36:48 +03009#include <command.h>
Simon Glass9d922452017-05-17 17:18:03 -060010#include <dm.h>
Simon Glass52559322019-11-14 12:57:46 -070011#include <init.h>
Chris Zankel7e270ec2016-08-10 18:36:48 +030012#include <dm/platform_data/net_ethoc.h>
Simon Glass9fb625c2019-08-01 09:46:51 -060013#include <env.h>
Chris Zankel7e270ec2016-08-10 18:36:48 +030014#include <linux/ctype.h>
15#include <linux/string.h>
16#include <linux/stringify.h>
17#include <asm/global_data.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21/*
22 * Check board idendity.
23 * (Print information about the board to stdout.)
24 */
25
26
27#if defined(CONFIG_XTFPGA_LX60)
28const char *board = "XT_AV60";
29const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
30#elif defined(CONFIG_XTFPGA_LX110)
31const char *board = "XT_AV110";
32const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
33#elif defined(CONFIG_XTFPGA_LX200)
34const char *board = "XT_AV200";
35const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
36#elif defined(CONFIG_XTFPGA_ML605)
37const char *board = "XT_ML605";
38const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
39#elif defined(CONFIG_XTFPGA_KC705)
40const char *board = "XT_KC705";
41const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
42#else
43const char *board = "<unknown>";
44const char *description = "";
45#endif
46
47int checkboard(void)
48{
49 printf("Board: %s: %sTensilica bitstream\n", board, description);
50 return 0;
51}
52
Tom Rinie4c3ce72021-12-14 13:36:39 -050053unsigned long get_board_sys_clk(void)
Chris Zankel7e270ec2016-08-10 18:36:48 +030054{
55 /*
56 * Obtain CPU clock frequency from board and cache in global
57 * data structure (Hz). Return 0 on success (OK to continue),
58 * else non-zero (hang).
59 */
60
Tom Rini65cc0e22022-11-16 13:10:41 -050061#ifdef CFG_SYS_FPGAREG_FREQ
62 return (*(volatile unsigned long *)CFG_SYS_FPGAREG_FREQ);
Chris Zankel7e270ec2016-08-10 18:36:48 +030063#else
64 /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
Tom Rinie4c3ce72021-12-14 13:36:39 -050065 return 50000000;
Chris Zankel7e270ec2016-08-10 18:36:48 +030066#endif
Tom Rinie4c3ce72021-12-14 13:36:39 -050067}
68
69int board_postclk_init(void)
70{
71 gd->cpu_clk = get_board_sys_clk();
72
Chris Zankel7e270ec2016-08-10 18:36:48 +030073 return 0;
74}
75
76/*
77 * Miscellaneous late initializations.
78 * The environment has been set up, so we can set the Ethernet address.
79 */
80
81int misc_init_r(void)
82{
83#ifdef CONFIG_CMD_NET
84 /*
85 * Initialize ethernet environment variables and board info.
86 * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
87 */
88
Simon Glass00caae62017-08-03 12:22:12 -060089 char *s = env_get("ethaddr");
Chris Zankel7e270ec2016-08-10 18:36:48 +030090 if (s == 0) {
91 unsigned int x;
Tom Rinifb55ac22022-12-04 10:03:49 -050092 char s[] = __stringify(CFG_ETHBASE);
Tom Rini65cc0e22022-11-16 13:10:41 -050093 x = (*(volatile u32 *)CFG_SYS_FPGAREG_DIPSW)
Chris Zankel7e270ec2016-08-10 18:36:48 +030094 & FPGAREG_MAC_MASK;
95 sprintf(&s[15], "%02x", x);
Simon Glass382bee52017-08-03 12:22:09 -060096 env_set("ethaddr", s);
Chris Zankel7e270ec2016-08-10 18:36:48 +030097 }
98#endif /* CONFIG_CMD_NET */
99
100 return 0;
101}
102
Simon Glass20e442a2020-12-28 20:34:54 -0700103U_BOOT_DRVINFO(sysreset) = {
Chris Zankel7e270ec2016-08-10 18:36:48 +0300104 .name = "xtfpga_sysreset",
105};
106
107static struct ethoc_eth_pdata ethoc_pdata = {
108 .eth_pdata = {
Tom Rini65cc0e22022-11-16 13:10:41 -0500109 .iobase = CFG_SYS_ETHOC_BASE,
Chris Zankel7e270ec2016-08-10 18:36:48 +0300110 },
Tom Rini65cc0e22022-11-16 13:10:41 -0500111 .packet_base = CFG_SYS_ETHOC_BUFFER_ADDR,
Chris Zankel7e270ec2016-08-10 18:36:48 +0300112};
113
Simon Glass20e442a2020-12-28 20:34:54 -0700114U_BOOT_DRVINFO(ethoc) = {
Chris Zankel7e270ec2016-08-10 18:36:48 +0300115 .name = "ethoc",
Simon Glasscaa4daa2020-12-03 16:55:18 -0700116 .plat = &ethoc_pdata,
Chris Zankel7e270ec2016-08-10 18:36:48 +0300117};