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Anton Vorontsovfd6646c2009-01-08 04:26:12 +03001/*
2 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
3 * Copyright (C) 2008-2009 MontaVista Software, Inc.
4 *
5 * Authors: Tony Li <tony.li@freescale.com>
6 * Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Anton Vorontsovfd6646c2009-01-08 04:26:12 +03009 */
10
11#include <common.h>
12#include <pci.h>
13#include <mpc83xx.h>
14#include <asm/io.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#define PCIE_MAX_BUSES 2
19
Ilya Yanokbab00b92010-09-17 23:41:46 +020020static struct {
21 u32 base;
22 u32 size;
23} mpc83xx_pcie_cfg_space[] = {
24 {
25 .base = CONFIG_SYS_PCIE1_CFG_BASE,
26 .size = CONFIG_SYS_PCIE1_CFG_SIZE,
27 },
28#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
29 {
30 .base = CONFIG_SYS_PCIE2_CFG_BASE,
31 .size = CONFIG_SYS_PCIE2_CFG_SIZE,
32 },
33#endif
34};
35
Anton Vorontsovfd6646c2009-01-08 04:26:12 +030036#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
37
Leo Liu10fa8d72011-01-19 19:50:47 +080038/* private structure for mpc83xx pcie hose */
39static struct mpc83xx_pcie_priv {
40 u8 index;
41} pcie_priv[PCIE_MAX_BUSES] = {
42 {
43 /* pcie controller 1 */
44 .index = 0,
45 },
46 {
47 /* pcie controller 2 */
48 .index = 1,
49 },
50};
51
Anton Vorontsovfd6646c2009-01-08 04:26:12 +030052static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
53{
54 int bus = PCI_BUS(dev) - hose->first_busno;
55 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
Leo Liu10fa8d72011-01-19 19:50:47 +080056 struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
57 pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
Anton Vorontsovfd6646c2009-01-08 04:26:12 +030058 struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
59 u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
60 u32 dev_base = bus << 24 | devfn << 16;
61
62 if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
63 return -1;
64 /*
65 * Workaround for the HW bug: for Type 0 configure transactions the
66 * PCI-E controller does not check the device number bits and just
67 * assumes that the device number bits are 0.
68 */
69 if (devfn & 0xf8)
70 return -1;
71
72 out_le32(&out_win->tarl, dev_base);
73 return 0;
74}
75
76#define cfg_read(val, addr, type, op) \
77 do { *val = op((type)(addr)); } while (0)
78#define cfg_write(val, addr, type, op) \
79 do { op((type *)(addr), (val)); } while (0)
80
Anton Vorontsovb24a99f2009-02-19 18:20:44 +030081#define cfg_read_err(val) do { *val = -1; } while (0)
82#define cfg_write_err(val) do { } while (0)
83
Anton Vorontsovfd6646c2009-01-08 04:26:12 +030084#define PCIE_OP(rw, size, type, op) \
85static int pcie_##rw##_config_##size(struct pci_controller *hose, \
86 pci_dev_t dev, int offset, \
87 type val) \
88{ \
89 int ret; \
90 \
91 ret = mpc83xx_pcie_remap_cfg(hose, dev); \
Anton Vorontsovb24a99f2009-02-19 18:20:44 +030092 if (ret) { \
93 cfg_##rw##_err(val); \
94 return ret; \
95 } \
Anton Vorontsovfd6646c2009-01-08 04:26:12 +030096 cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
97 return 0; \
98}
99
100PCIE_OP(read, byte, u8 *, in_8)
101PCIE_OP(read, word, u16 *, in_le16)
102PCIE_OP(read, dword, u32 *, in_le32)
103PCIE_OP(write, byte, u8, out_8)
104PCIE_OP(write, word, u16, out_le16)
105PCIE_OP(write, dword, u32, out_le32)
106
107static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
108 u8 link)
109{
110 extern void disable_addr_trans(void); /* start.S */
111 static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300112 struct pci_controller *hose = &pcie_hose[bus];
113 int i;
114
115 /*
116 * There are no spare BATs to remap all PCI-E windows for U-Boot, so
117 * disable translations. In general, this is not great solution, and
118 * that's why we don't register PCI-E hoses by default.
119 */
120 disable_addr_trans();
121
122 for (i = 0; i < 2; i++, reg++) {
123 if (reg->size == 0)
124 break;
125
126 hose->regions[i] = *reg;
127 hose->region_count++;
128 }
129
130 i = hose->region_count++;
131 hose->regions[i].bus_start = 0;
132 hose->regions[i].phys_start = 0;
133 hose->regions[i].size = gd->ram_size;
Kumar Galaff4e66e2009-02-06 09:49:31 -0600134 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300135
136 i = hose->region_count++;
137 hose->regions[i].bus_start = CONFIG_SYS_IMMR;
138 hose->regions[i].phys_start = CONFIG_SYS_IMMR;
139 hose->regions[i].size = 0x100000;
Kumar Galaff4e66e2009-02-06 09:49:31 -0600140 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300141
Anton Vorontsove2d72ba2009-02-19 18:20:42 +0300142 hose->first_busno = pci_last_busno() + 1;
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300143 hose->last_busno = 0xff;
144
Kim Phillips654d49b2010-09-22 15:31:01 -0500145 hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300146
Leo Liu10fa8d72011-01-19 19:50:47 +0800147 hose->priv_data = &pcie_priv[bus];
148
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300149 pci_set_ops(hose,
150 pcie_read_config_byte,
151 pcie_read_config_word,
152 pcie_read_config_dword,
153 pcie_write_config_byte,
154 pcie_write_config_word,
155 pcie_write_config_dword);
156
157 if (!link)
158 hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
159
160 pci_register_hose(hose);
161
162#ifdef CONFIG_PCI_SCAN_SHOW
163 printf("PCI: Bus Dev VenId DevId Class Int\n");
164#endif
165 /*
166 * Hose scan.
167 */
168 hose->last_busno = pci_hose_scan(hose);
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300169}
170
171#else
172
173static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
174 u8 link) {}
175
176#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
177
178static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
179{
180 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
181 pex83xx_t *pex = &immr->pciexp[bus];
182 struct pex_outbound_window *out_win;
183 struct pex_inbound_window *in_win;
184 void *hose_cfg_base;
185 unsigned int ram_sz;
186 unsigned int barl;
187 unsigned int tar;
188 u16 reg16;
189 int i;
190
191 /* Enable pex csb bridge inbound & outbound transactions */
192 out_le32(&pex->bridge.pex_csb_ctrl,
193 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
194 PEX_CSB_CTRL_IBPIOE);
195
196 /* Enable bridge outbound */
197 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
198 PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
199 PEX_CSB_OBCTRL_CFGWE);
200
201 out_win = &pex->bridge.pex_outbound_win[0];
Ilya Yanokbab00b92010-09-17 23:41:46 +0200202 out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
203 mpc83xx_pcie_cfg_space[bus].size);
204 out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300205 out_le32(&out_win->tarl, 0);
206 out_le32(&out_win->tarh, 0);
207
Baidu Boy054289f2010-11-29 21:10:45 +0800208 for (i = 0; i < 2; i++) {
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300209 u32 ar;
210
Baidu Boy054289f2010-11-29 21:10:45 +0800211 if (reg[i].size == 0)
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300212 break;
213
214 out_win = &pex->bridge.pex_outbound_win[i + 1];
Baidu Boy054289f2010-11-29 21:10:45 +0800215 out_le32(&out_win->bar, reg[i].phys_start);
216 out_le32(&out_win->tarl, reg[i].bus_start);
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300217 out_le32(&out_win->tarh, 0);
Baidu Boy054289f2010-11-29 21:10:45 +0800218 ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
219 if (reg[i].flags & PCI_REGION_IO)
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300220 ar |= PEX_OWAR_TYPE_IO;
221 else
222 ar |= PEX_OWAR_TYPE_MEM;
223 out_le32(&out_win->ar, ar);
224 }
225
226 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
227
228 ram_sz = gd->ram_size;
229 barl = 0;
230 tar = 0;
231 i = 0;
232 while (ram_sz > 0) {
233 in_win = &pex->bridge.pex_inbound_win[i];
234 out_le32(&in_win->barl, barl);
235 out_le32(&in_win->barh, 0x0);
236 out_le32(&in_win->tar, tar);
237 if (ram_sz >= 0x10000000) {
238 /* The maxium windows size is 256M */
239 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
240 PEX_IWAR_TYPE_PF | 0x0FFFF000);
241 barl += 0x10000000;
242 tar += 0x10000000;
243 ram_sz -= 0x10000000;
244 } else {
245 /* The UM is not clear here.
246 * So, round up to even Mb boundary */
247
248 ram_sz = ram_sz >> (20 +
249 ((ram_sz & 0xFFFFF) ? 1 : 0));
250 if (!(ram_sz % 2))
251 ram_sz -= 1;
252 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
253 PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
254 ram_sz = 0;
255 }
256 i++;
257 }
258
259 in_win = &pex->bridge.pex_inbound_win[i];
260 out_le32(&in_win->barl, CONFIG_SYS_IMMR);
261 out_le32(&in_win->barh, 0);
262 out_le32(&in_win->tar, CONFIG_SYS_IMMR);
263 out_le32(&in_win->ar, PEX_IWAR_EN |
264 PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
265
266 /* Enable the host virtual INTX interrupts */
267 out_le32(&pex->bridge.pex_int_axi_misc_enb,
268 in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
269
270 /* Hose configure header is memory-mapped */
271 hose_cfg_base = (void *)pex;
272
273 get_clocks();
274 /* Configure the PCIE controller core clock ratio */
275 out_le32(hose_cfg_base + PEX_GCLK_RATIO,
Simon Glassc6731fe2012-12-13 20:48:47 +0000276 (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
277 / 1000000) * 16) / 333);
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300278 udelay(1000000);
279
280 /* Do Type 1 bridge configuration */
281 out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
282 out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
283 out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
284
285 /*
286 * Write to Command register
287 */
288 reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
289 reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
290 PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
291 out_le16(hose_cfg_base + PCI_COMMAND, reg16);
292
293 /*
294 * Clear non-reserved bits in status register.
295 */
296 out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
297 out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
298 out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
299
300 printf("PCIE%d: ", bus);
301
Roy Zangce24f872012-12-10 19:02:59 +0800302#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
303#define PCI_LTSSM_L0 0x16 /* L0 state */
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300304 reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
305 if (reg16 >= PCI_LTSSM_L0)
306 printf("link\n");
307 else
308 printf("No link\n");
309
310 mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
311}
312
313/*
314 * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
315 * must have been set to cover all of the requested regions.
316 */
Peter Tyser6aa3d3b2010-09-14 19:13:50 -0500317void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300318{
319 int i;
320
321 /*
322 * Release PCI RST Output signal.
323 * Power on to RST high must be at least 100 ms as per PCI spec.
Peter Tyser6aa3d3b2010-09-14 19:13:50 -0500324 * On warm boots only 1 ms is required, but we play it safe.
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300325 */
Peter Tyser6aa3d3b2010-09-14 19:13:50 -0500326 udelay(100000);
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300327
Ilya Yanokbab00b92010-09-17 23:41:46 +0200328 if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
329 printf("Second PCIE host contoller not configured!\n");
330 num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
331 }
332
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300333 for (i = 0; i < num_buses; i++)
334 mpc83xx_pcie_init_bus(i, reg[i]);
335}