Blame - board/overo/overo.h - platform/external/u-boot

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Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	1	/*
				2	* (C) Copyright 2008
				3	* Steve Sakoman <steve@sakoman.com>
				4	*
				5	* See file CREDITS for list of people who contributed to this
				6	* project.
				7	*
				8	* This program is free software; you can redistribute it and/or
				9	* modify it under the terms of the GNU General Public License as
				10	* published by the Free Software Foundation; either version 2 of
				11	* the License, or (at your option) any later version.
				12	*
				13	* This program is distributed in the hope that it will be useful,
				14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
				15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				16	* GNU General Public License for more details.
				17	*
				18	* You should have received a copy of the GNU General Public License
				19	* along with this program; if not, write to the Free Software
				20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
				21	* MA 02111-1307 USA
				22	*/
				23	#ifndef _OVERO_H_
				24	#define _OVERO_H_
				25
				26	const omap3_sysinfo sysinfo = {
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	27	DDR_STACKED,
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	28	"Gumstix Overo board",
				29	#if defined(CONFIG_ENV_IS_IN_ONENAND)
				30	"OneNAND",
				31	#else
				32	"NAND",
				33	#endif
				34	};
				35
				36	/*
				37	* IEN - Input Enable
				38	* IDIS - Input Disable
				39	* PTD - Pull type Down
				40	* PTU - Pull type Up
				41	* DIS - Pull type selection is inactive
				42	* EN - Pull type selection is active
				43	* M0 - Mode 0
				44	* The commented string gives the final mux configuration for that pin
				45	*/
				46	#define MUX_OVERO() \
				47	/SDRC/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	48	MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) /SDRC_D0/\
				49	MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) /SDRC_D1/\
				50	MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) /SDRC_D2/\
				51	MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) /SDRC_D3/\
				52	MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) /SDRC_D4/\
				53	MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) /SDRC_D5/\
				54	MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) /SDRC_D6/\
				55	MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) /SDRC_D7/\
				56	MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) /SDRC_D8/\
				57	MUX_VAL(CP(SDRC_D9), (IEN \| PTD \| DIS \| M0)) /SDRC_D9/\
				58	MUX_VAL(CP(SDRC_D10), (IEN \| PTD \| DIS \| M0)) /SDRC_D10/\
				59	MUX_VAL(CP(SDRC_D11), (IEN \| PTD \| DIS \| M0)) /SDRC_D11/\
				60	MUX_VAL(CP(SDRC_D12), (IEN \| PTD \| DIS \| M0)) /SDRC_D12/\
				61	MUX_VAL(CP(SDRC_D13), (IEN \| PTD \| DIS \| M0)) /SDRC_D13/\
				62	MUX_VAL(CP(SDRC_D14), (IEN \| PTD \| DIS \| M0)) /SDRC_D14/\
				63	MUX_VAL(CP(SDRC_D15), (IEN \| PTD \| DIS \| M0)) /SDRC_D15/\
				64	MUX_VAL(CP(SDRC_D16), (IEN \| PTD \| DIS \| M0)) /SDRC_D16/\
				65	MUX_VAL(CP(SDRC_D17), (IEN \| PTD \| DIS \| M0)) /SDRC_D17/\
				66	MUX_VAL(CP(SDRC_D18), (IEN \| PTD \| DIS \| M0)) /SDRC_D18/\
				67	MUX_VAL(CP(SDRC_D19), (IEN \| PTD \| DIS \| M0)) /SDRC_D19/\
				68	MUX_VAL(CP(SDRC_D20), (IEN \| PTD \| DIS \| M0)) /SDRC_D20/\
				69	MUX_VAL(CP(SDRC_D21), (IEN \| PTD \| DIS \| M0)) /SDRC_D21/\
				70	MUX_VAL(CP(SDRC_D22), (IEN \| PTD \| DIS \| M0)) /SDRC_D22/\
				71	MUX_VAL(CP(SDRC_D23), (IEN \| PTD \| DIS \| M0)) /SDRC_D23/\
				72	MUX_VAL(CP(SDRC_D24), (IEN \| PTD \| DIS \| M0)) /SDRC_D24/\
				73	MUX_VAL(CP(SDRC_D25), (IEN \| PTD \| DIS \| M0)) /SDRC_D25/\
				74	MUX_VAL(CP(SDRC_D26), (IEN \| PTD \| DIS \| M0)) /SDRC_D26/\
				75	MUX_VAL(CP(SDRC_D27), (IEN \| PTD \| DIS \| M0)) /SDRC_D27/\
				76	MUX_VAL(CP(SDRC_D28), (IEN \| PTD \| DIS \| M0)) /SDRC_D28/\
				77	MUX_VAL(CP(SDRC_D29), (IEN \| PTD \| DIS \| M0)) /SDRC_D29/\
				78	MUX_VAL(CP(SDRC_D30), (IEN \| PTD \| DIS \| M0)) /SDRC_D30/\
				79	MUX_VAL(CP(SDRC_D31), (IEN \| PTD \| DIS \| M0)) /SDRC_D31/\
				80	MUX_VAL(CP(SDRC_CLK), (IEN \| PTD \| DIS \| M0)) /SDRC_CLK/\
				81	MUX_VAL(CP(SDRC_DQS0), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS0/\
				82	MUX_VAL(CP(SDRC_DQS1), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS1/\
				83	MUX_VAL(CP(SDRC_DQS2), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS2/\
				84	MUX_VAL(CP(SDRC_DQS3), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS3/\
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	85	/GPMC/\
Olof Johansson	df38262	2009-09-29 10:22:45 -0400	[diff] [blame]	86	MUX_VAL(CP(GPMC_A1), (IDIS \| PTU \| EN \| M0)) /GPMC_A1/\
				87	MUX_VAL(CP(GPMC_A2), (IDIS \| PTU \| EN \| M0)) /GPMC_A2/\
				88	MUX_VAL(CP(GPMC_A3), (IDIS \| PTU \| EN \| M0)) /GPMC_A3/\
				89	MUX_VAL(CP(GPMC_A4), (IDIS \| PTU \| EN \| M0)) /GPMC_A4/\
				90	MUX_VAL(CP(GPMC_A5), (IDIS \| PTU \| EN \| M0)) /GPMC_A5/\
				91	MUX_VAL(CP(GPMC_A6), (IDIS \| PTU \| EN \| M0)) /GPMC_A6/\
				92	MUX_VAL(CP(GPMC_A7), (IDIS \| PTU \| EN \| M0)) /GPMC_A7/\
				93	MUX_VAL(CP(GPMC_A8), (IDIS \| PTU \| EN \| M0)) /GPMC_A8/\
				94	MUX_VAL(CP(GPMC_A9), (IDIS \| PTU \| EN \| M0)) /GPMC_A9/\
				95	MUX_VAL(CP(GPMC_A10), (IDIS \| PTU \| EN \| M0)) /GPMC_A10/\
				96	MUX_VAL(CP(GPMC_D0), (IEN \| PTU \| EN \| M0)) /GPMC_D0/\
				97	MUX_VAL(CP(GPMC_D1), (IEN \| PTU \| EN \| M0)) /GPMC_D1/\
				98	MUX_VAL(CP(GPMC_D2), (IEN \| PTU \| EN \| M0)) /GPMC_D2/\
				99	MUX_VAL(CP(GPMC_D3), (IEN \| PTU \| EN \| M0)) /GPMC_D3/\
				100	MUX_VAL(CP(GPMC_D4), (IEN \| PTU \| EN \| M0)) /GPMC_D4/\
				101	MUX_VAL(CP(GPMC_D5), (IEN \| PTU \| EN \| M0)) /GPMC_D5/\
				102	MUX_VAL(CP(GPMC_D6), (IEN \| PTU \| EN \| M0)) /GPMC_D6/\
				103	MUX_VAL(CP(GPMC_D7), (IEN \| PTU \| EN \| M0)) /GPMC_D7/\
				104	MUX_VAL(CP(GPMC_D8), (IEN \| PTU \| EN \| M0)) /GPMC_D8/\
				105	MUX_VAL(CP(GPMC_D9), (IEN \| PTU \| EN \| M0)) /GPMC_D9/\
				106	MUX_VAL(CP(GPMC_D10), (IEN \| PTU \| EN \| M0)) /GPMC_D10/\
				107	MUX_VAL(CP(GPMC_D11), (IEN \| PTU \| EN \| M0)) /GPMC_D11/\
				108	MUX_VAL(CP(GPMC_D12), (IEN \| PTU \| EN \| M0)) /GPMC_D12/\
				109	MUX_VAL(CP(GPMC_D13), (IEN \| PTU \| EN \| M0)) /GPMC_D13/\
				110	MUX_VAL(CP(GPMC_D14), (IEN \| PTU \| EN \| M0)) /GPMC_D14/\
				111	MUX_VAL(CP(GPMC_D15), (IEN \| PTU \| EN \| M0)) /GPMC_D15/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	112	MUX_VAL(CP(GPMC_NCS0), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS0/\
				113	MUX_VAL(CP(GPMC_NCS1), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS1/\
				114	MUX_VAL(CP(GPMC_NCS2), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS2/\
				115	MUX_VAL(CP(GPMC_NCS3), (IEN \| PTU \| EN \| M4)) /GPIO_54/\
				116	/* - MMC1_WP*/\
				117	MUX_VAL(CP(GPMC_NCS4), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS4/\
Olof Johansson	df38262	2009-09-29 10:22:45 -0400	[diff] [blame]	118	MUX_VAL(CP(GPMC_NCS5), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS5/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	119	MUX_VAL(CP(GPMC_NCS6), (IEN \| PTD \| DIS \| M0)) /GPMC_nCS6/\
				120	MUX_VAL(CP(GPMC_NCS7), (IEN \| PTU \| EN \| M0)) /GPMC_nCS7/\
				121	MUX_VAL(CP(GPMC_NBE1), (IEN \| PTD \| DIS \| M0)) /GPMC_nCS3/\
Philip Balister	cdbc277	2011-09-14 12:50:12 -0400	[diff] [blame]	122	MUX_VAL(CP(GPMC_CLK), (IEN \| PTU \| EN \| M0)) /GPMC_CLK/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	123	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nADV_ALE/\
				124	MUX_VAL(CP(GPMC_NOE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nOE/\
				125	MUX_VAL(CP(GPMC_NWE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nWE/\
				126	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nBE0_CLE/\
				127	MUX_VAL(CP(GPMC_NWP), (IEN \| PTD \| DIS \| M0)) /GPMC_nWP/\
				128	MUX_VAL(CP(GPMC_WAIT0), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT0/\
				129	MUX_VAL(CP(GPMC_WAIT1), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT1/\
Olof Johansson	df38262	2009-09-29 10:22:45 -0400	[diff] [blame]	130	MUX_VAL(CP(GPMC_WAIT2), (IEN \| PTU \| EN \| M4)) /GPIO_64/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	131	/* - SMSC911X_NRES*/\
Steve Sakoman	ba9a11e	2010-08-12 21:07:02 -0700	[diff] [blame]	132	MUX_VAL(CP(GPMC_WAIT3), (IEN \| PTU \| DIS \| M4)) /GPIO_65/\
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	133	/DSS/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	134	MUX_VAL(CP(DSS_PCLK), (IDIS \| PTD \| DIS \| M0)) /DSS_PCLK/\
				135	MUX_VAL(CP(DSS_HSYNC), (IDIS \| PTD \| DIS \| M0)) /DSS_HSYNC/\
				136	MUX_VAL(CP(DSS_VSYNC), (IDIS \| PTD \| DIS \| M0)) /DSS_VSYNC/\
				137	MUX_VAL(CP(DSS_ACBIAS), (IDIS \| PTD \| DIS \| M0)) /DSS_ACBIAS/\
				138	MUX_VAL(CP(DSS_DATA0), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA0/\
				139	MUX_VAL(CP(DSS_DATA1), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA1/\
				140	MUX_VAL(CP(DSS_DATA2), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA2/\
				141	MUX_VAL(CP(DSS_DATA3), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA3/\
				142	MUX_VAL(CP(DSS_DATA4), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA4/\
				143	MUX_VAL(CP(DSS_DATA5), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA5/\
				144	MUX_VAL(CP(DSS_DATA6), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA6/\
				145	MUX_VAL(CP(DSS_DATA7), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA7/\
				146	MUX_VAL(CP(DSS_DATA8), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA8/\
				147	MUX_VAL(CP(DSS_DATA9), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA9/\
				148	MUX_VAL(CP(DSS_DATA10), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA10/\
				149	MUX_VAL(CP(DSS_DATA11), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA11/\
				150	MUX_VAL(CP(DSS_DATA12), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA12/\
				151	MUX_VAL(CP(DSS_DATA13), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA13/\
				152	MUX_VAL(CP(DSS_DATA14), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA14/\
				153	MUX_VAL(CP(DSS_DATA15), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA15/\
				154	MUX_VAL(CP(DSS_DATA16), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA16/\
				155	MUX_VAL(CP(DSS_DATA17), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA17/\
				156	MUX_VAL(CP(DSS_DATA18), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA18/\
				157	MUX_VAL(CP(DSS_DATA19), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA19/\
				158	MUX_VAL(CP(DSS_DATA20), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA20/\
				159	MUX_VAL(CP(DSS_DATA21), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA21/\
				160	MUX_VAL(CP(DSS_DATA22), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA22/\
				161	MUX_VAL(CP(DSS_DATA23), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA23/\
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	162	/CAMERA/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	163	MUX_VAL(CP(CAM_HS), (IEN \| PTU \| EN \| M0)) /CAM_HS /\
				164	MUX_VAL(CP(CAM_VS), (IEN \| PTU \| EN \| M0)) /CAM_VS /\
				165	MUX_VAL(CP(CAM_XCLKA), (IDIS \| PTD \| DIS \| M0)) /CAM_XCLKA/\
				166	MUX_VAL(CP(CAM_PCLK), (IEN \| PTU \| EN \| M0)) /CAM_PCLK/\
				167	MUX_VAL(CP(CAM_FLD), (IDIS \| PTD \| DIS \| M4)) /CAM_FLD/\
				168	MUX_VAL(CP(CAM_D0), (IEN \| PTD \| DIS \| M0)) /CAM_D0/\
				169	MUX_VAL(CP(CAM_D1), (IEN \| PTD \| DIS \| M0)) /CAM_D1/\
				170	MUX_VAL(CP(CAM_D2), (IEN \| PTD \| DIS \| M0)) /CAM_D2/\
				171	MUX_VAL(CP(CAM_D3), (IEN \| PTD \| DIS \| M0)) /CAM_D3/\
				172	MUX_VAL(CP(CAM_D4), (IEN \| PTD \| DIS \| M0)) /CAM_D4/\
				173	MUX_VAL(CP(CAM_D5), (IEN \| PTD \| DIS \| M0)) /CAM_D5/\
				174	MUX_VAL(CP(CAM_D6), (IEN \| PTD \| DIS \| M0)) /CAM_D6/\
				175	MUX_VAL(CP(CAM_D7), (IEN \| PTD \| DIS \| M0)) /CAM_D7/\
				176	MUX_VAL(CP(CAM_D8), (IEN \| PTD \| DIS \| M0)) /CAM_D8/\
				177	MUX_VAL(CP(CAM_D9), (IEN \| PTD \| DIS \| M0)) /CAM_D9/\
				178	MUX_VAL(CP(CAM_D10), (IEN \| PTD \| DIS \| M0)) /CAM_D10/\
				179	MUX_VAL(CP(CAM_D11), (IEN \| PTD \| DIS \| M0)) /CAM_D11/\
				180	MUX_VAL(CP(CAM_XCLKB), (IDIS \| PTD \| DIS \| M0)) /CAM_XCLKB/\
				181	MUX_VAL(CP(CAM_WEN), (IEN \| PTD \| DIS \| M0)) /CAM_WEN/\
				182	MUX_VAL(CP(CAM_STROBE), (IDIS \| PTD \| DIS \| M0)) /CAM_STROBE/\
Steve Sakoman	c2d5b34	2010-08-12 15:13:02 -0700	[diff] [blame]	183	MUX_VAL(CP(CSI2_DX0), (IEN \| PTD \| EN \| M4)) /GPIO_112/\
				184	MUX_VAL(CP(CSI2_DY0), (IEN \| PTD \| EN \| M4)) /GPIO_113/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	185	MUX_VAL(CP(CSI2_DX1), (IEN \| PTD \| EN \| M4)) /GPIO_114/\
				186	/* - PEN_DOWN*/\
Steve Sakoman	c2d5b34	2010-08-12 15:13:02 -0700	[diff] [blame]	187	MUX_VAL(CP(CSI2_DY1), (IEN \| PTD \| EN \| M4)) /GPIO_115/\
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	188	/Audio Interface /\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	189	MUX_VAL(CP(MCBSP2_FSX), (IEN \| PTD \| DIS \| M0)) /McBSP2_FSX/\
				190	MUX_VAL(CP(MCBSP2_CLKX), (IEN \| PTD \| DIS \| M0)) /McBSP2_CLKX/\
				191	MUX_VAL(CP(MCBSP2_DR), (IEN \| PTD \| DIS \| M0)) /McBSP2_DR/\
				192	MUX_VAL(CP(MCBSP2_DX), (IDIS \| PTD \| DIS \| M0)) /McBSP2_DX/\
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	193	/Expansion card /\
Steve Sakoman	9314961	2010-02-16 10:00:45 -0800	[diff] [blame]	194	MUX_VAL(CP(MMC1_CLK), (IEN \| PTU \| EN \| M0)) /MMC1_CLK/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	195	MUX_VAL(CP(MMC1_CMD), (IEN \| PTU \| EN \| M0)) /MMC1_CMD/\
				196	MUX_VAL(CP(MMC1_DAT0), (IEN \| PTU \| EN \| M0)) /MMC1_DAT0/\
				197	MUX_VAL(CP(MMC1_DAT1), (IEN \| PTU \| EN \| M0)) /MMC1_DAT1/\
				198	MUX_VAL(CP(MMC1_DAT2), (IEN \| PTU \| EN \| M0)) /MMC1_DAT2/\
				199	MUX_VAL(CP(MMC1_DAT3), (IEN \| PTU \| EN \| M0)) /MMC1_DAT3/\
				200	MUX_VAL(CP(MMC1_DAT4), (IEN \| PTU \| EN \| M0)) /MMC1_DAT4/\
				201	MUX_VAL(CP(MMC1_DAT5), (IEN \| PTU \| EN \| M0)) /MMC1_DAT5/\
				202	MUX_VAL(CP(MMC1_DAT6), (IEN \| PTU \| EN \| M0)) /MMC1_DAT6/\
				203	MUX_VAL(CP(MMC1_DAT7), (IEN \| PTU \| EN \| M0)) /MMC1_DAT7/\
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	204	/Wireless LAN /\
Steve Sakoman	a06e162	2010-08-24 10:37:29 -0700	[diff] [blame]	205	MUX_VAL(CP(MMC2_CLK), (IEN \| PTU \| EN \| M4)) /GPIO_130/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	206	MUX_VAL(CP(MMC2_CMD), (IEN \| PTU \| EN \| M0)) /MMC2_CMD/\
				207	MUX_VAL(CP(MMC2_DAT0), (IEN \| PTU \| EN \| M0)) /MMC2_DAT0/\
				208	MUX_VAL(CP(MMC2_DAT1), (IEN \| PTU \| EN \| M0)) /MMC2_DAT1/\
				209	MUX_VAL(CP(MMC2_DAT2), (IEN \| PTU \| EN \| M0)) /MMC2_DAT2/\
				210	MUX_VAL(CP(MMC2_DAT3), (IEN \| PTU \| EN \| M0)) /MMC2_DAT3/\
				211	MUX_VAL(CP(MMC2_DAT4), (IEN \| PTU \| EN \| M1)) /MMC2_DIR_DAT0/\
				212	MUX_VAL(CP(MMC2_DAT5), (IEN \| PTU \| EN \| M1)) /MMC2_DIR_DAT1/\
				213	MUX_VAL(CP(MMC2_DAT6), (IEN \| PTU \| EN \| M1)) /MMC2_DIR_CMD/\
Steve Sakoman	a06e162	2010-08-24 10:37:29 -0700	[diff] [blame]	214	MUX_VAL(CP(MMC2_DAT7), (IEN \| PTU \| EN \| M4)) /GPIO_139/\
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	215	/Bluetooth/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	216	MUX_VAL(CP(MCBSP3_DX), (IEN \| PTD \| DIS \| M1)) /UART2_CTS/\
				217	MUX_VAL(CP(MCBSP3_DR), (IDIS \| PTD \| DIS \| M1)) /UART2_RTS/\
				218	MUX_VAL(CP(MCBSP3_CLKX), (IDIS \| PTD \| DIS \| M1)) /UART2_TX/\
				219	MUX_VAL(CP(MCBSP3_FSX), (IEN \| PTD \| DIS \| M1)) /UART2_RX/\
				220	MUX_VAL(CP(UART2_CTS), (IEN \| PTD \| DIS \| M4)) /GPIO_144 - LCD_EN/\
				221	MUX_VAL(CP(UART2_RTS), (IEN \| PTD \| DIS \| M4)) /GPIO_145/\
				222	MUX_VAL(CP(UART2_TX), (IEN \| PTD \| DIS \| M4)) /GPIO_146/\
				223	MUX_VAL(CP(UART2_RX), (IEN \| PTD \| DIS \| M4)) /GPIO_147/\
				224	MUX_VAL(CP(UART1_TX), (IDIS \| PTD \| DIS \| M0)) /UART1_TX/\
				225	MUX_VAL(CP(UART1_RTS), (IEN \| PTU \| DIS \| M4)) /GPIO_149/ \
				226	MUX_VAL(CP(UART1_CTS), (IEN \| PTU \| DIS \| M4)) /GPIO_150-MMC3_WP/\
				227	MUX_VAL(CP(UART1_RX), (IEN \| PTD \| DIS \| M0)) /UART1_RX/\
				228	MUX_VAL(CP(MCBSP4_CLKX), (IEN \| PTD \| DIS \| M0)) /McBSP4_CLKX/\
				229	MUX_VAL(CP(MCBSP4_DR), (IEN \| PTD \| DIS \| M0)) /McBSP4_DR/\
				230	MUX_VAL(CP(MCBSP4_DX), (IEN \| PTD \| DIS \| M0)) /McBSP4_DX/\
				231	MUX_VAL(CP(MCBSP4_FSX), (IEN \| PTD \| DIS \| M0)) /McBSP4_FSX/\
				232	MUX_VAL(CP(MCBSP1_CLKR), (IEN \| PTD \| DIS \| M0)) /McBSP1_CLKR/\
				233	MUX_VAL(CP(MCBSP1_FSR), (IEN \| PTD \| DIS \| M0)) /McBSP1_FSR/\
				234	MUX_VAL(CP(MCBSP1_DX), (IEN \| PTD \| DIS \| M0)) /McBSP1_DX/\
				235	MUX_VAL(CP(MCBSP1_DR), (IEN \| PTD \| DIS \| M0)) /McBSP1_DR/\
				236	MUX_VAL(CP(MCBSP_CLKS), (IEN \| PTU \| DIS \| M0)) /McBSP_CLKS/\
				237	MUX_VAL(CP(MCBSP1_FSX), (IEN \| PTD \| DIS \| M0)) /McBSP1_FSX/\
				238	MUX_VAL(CP(MCBSP1_CLKX), (IEN \| PTD \| DIS \| M0)) /McBSP1_CLKX/\
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	239	/Serial Interface/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	240	MUX_VAL(CP(UART3_CTS_RCTX), (IEN \| PTD \| EN \| M0)) /UART3_CTS_RCTX/\
				241	MUX_VAL(CP(UART3_RTS_SD), (IEN \| PTU \| EN \| M4)) /GPIO_164 W2W_/\
				242	/* BT_NRESET*/\
				243	MUX_VAL(CP(UART3_RX_IRRX), (IEN \| PTU \| EN \| M0)) /UART3_RX_IRRX/\
				244	MUX_VAL(CP(UART3_TX_IRTX), (IDIS \| PTD \| DIS \| M0)) /UART3_TX_IRTX/\
				245	MUX_VAL(CP(HSUSB0_CLK), (IEN \| PTD \| DIS \| M0)) /HSUSB0_CLK/\
				246	MUX_VAL(CP(HSUSB0_STP), (IDIS \| PTU \| EN \| M0)) /HSUSB0_STP/\
				247	MUX_VAL(CP(HSUSB0_DIR), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DIR/\
				248	MUX_VAL(CP(HSUSB0_NXT), (IEN \| PTD \| DIS \| M0)) /HSUSB0_NXT/\
				249	MUX_VAL(CP(HSUSB0_DATA0), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA0/\
				250	MUX_VAL(CP(HSUSB0_DATA1), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA1/\
				251	MUX_VAL(CP(HSUSB0_DATA2), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA2/\
				252	MUX_VAL(CP(HSUSB0_DATA3), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA3/\
				253	MUX_VAL(CP(HSUSB0_DATA4), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA4/\
				254	MUX_VAL(CP(HSUSB0_DATA5), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA5/\
				255	MUX_VAL(CP(HSUSB0_DATA6), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA6/\
				256	MUX_VAL(CP(HSUSB0_DATA7), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA7/\
				257	MUX_VAL(CP(I2C1_SCL), (IEN \| PTU \| EN \| M0)) /I2C1_SCL/\
				258	MUX_VAL(CP(I2C1_SDA), (IEN \| PTU \| EN \| M0)) /I2C1_SDA/\
				259	MUX_VAL(CP(I2C2_SCL), (IEN \| PTU \| EN \| M4)) /GPIO_168/\
				260	/* - USBH_CPEN*/\
				261	MUX_VAL(CP(I2C2_SDA), (IEN \| PTU \| EN \| M4)) /GPIO_183/\
				262	/* - USBH_RESET*/\
				263	MUX_VAL(CP(I2C3_SCL), (IEN \| PTU \| EN \| M0)) /I2C3_SCL/\
				264	MUX_VAL(CP(I2C3_SDA), (IEN \| PTU \| EN \| M0)) /I2C3_SDA/\
				265	MUX_VAL(CP(I2C4_SCL), (IEN \| PTU \| EN \| M0)) /I2C4_SCL/\
				266	MUX_VAL(CP(I2C4_SDA), (IEN \| PTU \| EN \| M0)) /I2C4_SDA/\
				267	MUX_VAL(CP(HDQ_SIO), (IDIS \| PTU \| EN \| M4)) /HDQ_SIO/\
				268	MUX_VAL(CP(MCSPI1_CLK), (IEN \| PTD \| DIS \| M0)) /McSPI1_CLK/\
				269	MUX_VAL(CP(MCSPI1_SIMO), (IEN \| PTD \| DIS \| M0)) /McSPI1_SIMO /\
				270	MUX_VAL(CP(MCSPI1_SOMI), (IEN \| PTD \| DIS \| M0)) /McSPI1_SOMI /\
				271	MUX_VAL(CP(MCSPI1_CS0), (IEN \| PTD \| EN \| M0)) /McSPI1_CS0/\
				272	MUX_VAL(CP(MCSPI1_CS1), (IDIS \| PTD \| EN \| M0)) /McSPI1_CS1/\
Olof Johansson	df38262	2009-09-29 10:22:45 -0400	[diff] [blame]	273	MUX_VAL(CP(MCSPI1_CS2), (IEN \| PTU \| DIS \| M4)) /GPIO_176 /\
				274	/* - LAN_INTR */\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	275	MUX_VAL(CP(MCSPI1_CS3), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA2/\
				276	MUX_VAL(CP(MCSPI2_CLK), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA7/\
				277	MUX_VAL(CP(MCSPI2_SIMO), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA4/\
				278	MUX_VAL(CP(MCSPI2_SOMI), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA5/\
				279	MUX_VAL(CP(MCSPI2_CS0), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA6/\
				280	MUX_VAL(CP(MCSPI2_CS1), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA3/\
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	281	/Control and debug /\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	282	MUX_VAL(CP(SYS_32K), (IEN \| PTD \| DIS \| M0)) /SYS_32K/\
				283	MUX_VAL(CP(SYS_CLKREQ), (IEN \| PTD \| DIS \| M0)) /SYS_CLKREQ/\
				284	MUX_VAL(CP(SYS_NIRQ), (IEN \| PTU \| EN \| M0)) /SYS_nIRQ/\
				285	MUX_VAL(CP(SYS_BOOT0), (IEN \| PTD \| DIS \| M4)) /GPIO_2/\
				286	MUX_VAL(CP(SYS_BOOT1), (IEN \| PTD \| DIS \| M4)) /GPIO_3 /\
				287	MUX_VAL(CP(SYS_BOOT2), (IEN \| PTD \| DIS \| M4)) /GPIO_4 - MMC1_WP/\
				288	MUX_VAL(CP(SYS_BOOT3), (IEN \| PTD \| DIS \| M4)) /GPIO_5/\
				289	MUX_VAL(CP(SYS_BOOT4), (IEN \| PTD \| DIS \| M4)) /GPIO_6/\
				290	MUX_VAL(CP(SYS_BOOT5), (IEN \| PTD \| DIS \| M4)) /GPIO_7/\
				291	MUX_VAL(CP(SYS_BOOT6), (IDIS \| PTD \| DIS \| M4)) /GPIO_8/\
				292	MUX_VAL(CP(SYS_OFF_MODE), (IEN \| PTD \| DIS \| M0)) /SYS_OFF_MODE/\
				293	MUX_VAL(CP(SYS_CLKOUT1), (IEN \| PTD \| DIS \| M0)) /SYS_CLKOUT1/\
				294	MUX_VAL(CP(SYS_CLKOUT2), (IEN \| PTU \| EN \| M4)) /GPIO_186/\
Steve Sakoman	9314961	2010-02-16 10:00:45 -0800	[diff] [blame]	295	MUX_VAL(CP(ETK_CLK_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_CLK/\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	296	MUX_VAL(CP(ETK_CTL_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_CMD/\
				297	MUX_VAL(CP(ETK_D0_ES2), (IEN \| PTU \| EN \| M4)) /GPIO_14/\
				298	MUX_VAL(CP(ETK_D1_ES2), (IEN \| PTD \| EN \| M4)) /GPIO_15 - X_GATE/\
				299	MUX_VAL(CP(ETK_D2_ES2), (IEN \| PTU \| EN \| M4)) /GPIO_16/\
				300	/* - W2W_NRESET*/\
				301	MUX_VAL(CP(ETK_D3_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT3/\
				302	MUX_VAL(CP(ETK_D4_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT0/\
				303	MUX_VAL(CP(ETK_D5_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT1/\
				304	MUX_VAL(CP(ETK_D6_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT2/\
				305	MUX_VAL(CP(ETK_D7_ES2), (IEN \| PTU \| EN \| M4)) /GPIO_21/\
				306	MUX_VAL(CP(ETK_D8_ES2), (IEN \| PTU \| EN \| M4)) /GPIO_22/\
				307	MUX_VAL(CP(ETK_D9_ES2), (IEN \| PTU \| EN \| M4)) /GPIO_23/\
				308	MUX_VAL(CP(ETK_D10_ES2), (IDIS \| PTD \| DIS \| M3)) /HSUSB2_CLK/\
				309	MUX_VAL(CP(ETK_D11_ES2), (IDIS \| PTD \| DIS \| M3)) /HSUSB2_STP/\
				310	MUX_VAL(CP(ETK_D12_ES2), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DIR/\
				311	MUX_VAL(CP(ETK_D13_ES2), (IEN \| PTD \| DIS \| M3)) /HSUSB2_NXT/\
				312	MUX_VAL(CP(ETK_D14_ES2), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA0/\
				313	MUX_VAL(CP(ETK_D15_ES2), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA1/\
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	314	/* die to die */\
Olof Johansson	fc9165f	2009-09-28 08:19:30 -0400	[diff] [blame]	315	MUX_VAL(CP(D2D_MCAD1), (IEN \| PTD \| EN \| M0)) /d2d_mcad1/\
				316	MUX_VAL(CP(D2D_MCAD2), (IEN \| PTD \| EN \| M0)) /d2d_mcad2/\
				317	MUX_VAL(CP(D2D_MCAD3), (IEN \| PTD \| EN \| M0)) /d2d_mcad3/\
				318	MUX_VAL(CP(D2D_MCAD4), (IEN \| PTD \| EN \| M0)) /d2d_mcad4/\
				319	MUX_VAL(CP(D2D_MCAD5), (IEN \| PTD \| EN \| M0)) /d2d_mcad5/\
				320	MUX_VAL(CP(D2D_MCAD6), (IEN \| PTD \| EN \| M0)) /d2d_mcad6/\
				321	MUX_VAL(CP(D2D_MCAD7), (IEN \| PTD \| EN \| M0)) /d2d_mcad7/\
				322	MUX_VAL(CP(D2D_MCAD8), (IEN \| PTD \| EN \| M0)) /d2d_mcad8/\
				323	MUX_VAL(CP(D2D_MCAD9), (IEN \| PTD \| EN \| M0)) /d2d_mcad9/\
				324	MUX_VAL(CP(D2D_MCAD10), (IEN \| PTD \| EN \| M0)) /d2d_mcad10/\
				325	MUX_VAL(CP(D2D_MCAD11), (IEN \| PTD \| EN \| M0)) /d2d_mcad11/\
				326	MUX_VAL(CP(D2D_MCAD12), (IEN \| PTD \| EN \| M0)) /d2d_mcad12/\
				327	MUX_VAL(CP(D2D_MCAD13), (IEN \| PTD \| EN \| M0)) /d2d_mcad13/\
				328	MUX_VAL(CP(D2D_MCAD14), (IEN \| PTD \| EN \| M0)) /d2d_mcad14/\
				329	MUX_VAL(CP(D2D_MCAD15), (IEN \| PTD \| EN \| M0)) /d2d_mcad15/\
				330	MUX_VAL(CP(D2D_MCAD16), (IEN \| PTD \| EN \| M0)) /d2d_mcad16/\
				331	MUX_VAL(CP(D2D_MCAD17), (IEN \| PTD \| EN \| M0)) /d2d_mcad17/\
				332	MUX_VAL(CP(D2D_MCAD18), (IEN \| PTD \| EN \| M0)) /d2d_mcad18/\
				333	MUX_VAL(CP(D2D_MCAD19), (IEN \| PTD \| EN \| M0)) /d2d_mcad19/\
				334	MUX_VAL(CP(D2D_MCAD20), (IEN \| PTD \| EN \| M0)) /d2d_mcad20/\
				335	MUX_VAL(CP(D2D_MCAD21), (IEN \| PTD \| EN \| M0)) /d2d_mcad21/\
				336	MUX_VAL(CP(D2D_MCAD22), (IEN \| PTD \| EN \| M0)) /d2d_mcad22/\
				337	MUX_VAL(CP(D2D_MCAD23), (IEN \| PTD \| EN \| M0)) /d2d_mcad23/\
				338	MUX_VAL(CP(D2D_MCAD24), (IEN \| PTD \| EN \| M0)) /d2d_mcad24/\
				339	MUX_VAL(CP(D2D_MCAD25), (IEN \| PTD \| EN \| M0)) /d2d_mcad25/\
				340	MUX_VAL(CP(D2D_MCAD26), (IEN \| PTD \| EN \| M0)) /d2d_mcad26/\
				341	MUX_VAL(CP(D2D_MCAD27), (IEN \| PTD \| EN \| M0)) /d2d_mcad27/\
				342	MUX_VAL(CP(D2D_MCAD28), (IEN \| PTD \| EN \| M0)) /d2d_mcad28/\
				343	MUX_VAL(CP(D2D_MCAD29), (IEN \| PTD \| EN \| M0)) /d2d_mcad29/\
				344	MUX_VAL(CP(D2D_MCAD30), (IEN \| PTD \| EN \| M0)) /d2d_mcad30/\
				345	MUX_VAL(CP(D2D_MCAD31), (IEN \| PTD \| EN \| M0)) /d2d_mcad31/\
				346	MUX_VAL(CP(D2D_MCAD32), (IEN \| PTD \| EN \| M0)) /d2d_mcad32/\
				347	MUX_VAL(CP(D2D_MCAD33), (IEN \| PTD \| EN \| M0)) /d2d_mcad33/\
				348	MUX_VAL(CP(D2D_MCAD34), (IEN \| PTD \| EN \| M0)) /d2d_mcad34/\
				349	MUX_VAL(CP(D2D_MCAD35), (IEN \| PTD \| EN \| M0)) /d2d_mcad35/\
				350	MUX_VAL(CP(D2D_MCAD36), (IEN \| PTD \| EN \| M0)) /d2d_mcad36/\
				351	MUX_VAL(CP(D2D_CLK26MI), (IEN \| PTD \| DIS \| M0)) /d2d_clk26mi/\
				352	MUX_VAL(CP(D2D_NRESPWRON), (IEN \| PTD \| EN \| M0)) /d2d_nrespwron/\
				353	MUX_VAL(CP(D2D_NRESWARM), (IEN \| PTU \| EN \| M0)) /d2d_nreswarm /\
				354	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN \| PTD \| DIS \| M0)) /d2d_arm9nirq /\
				355	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN \| PTD \| DIS \| M0)) /d2d_uma2p6fiq/\
				356	MUX_VAL(CP(D2D_SPINT), (IEN \| PTD \| EN \| M0)) /d2d_spint/\
				357	MUX_VAL(CP(D2D_FRINT), (IEN \| PTD \| EN \| M0)) /d2d_frint/\
				358	MUX_VAL(CP(D2D_DMAREQ0), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq0/\
				359	MUX_VAL(CP(D2D_DMAREQ1), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq1/\
				360	MUX_VAL(CP(D2D_DMAREQ2), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq2/\
				361	MUX_VAL(CP(D2D_DMAREQ3), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq3/\
				362	MUX_VAL(CP(D2D_N3GTRST), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtrst/\
				363	MUX_VAL(CP(D2D_N3GTDI), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtdi/\
				364	MUX_VAL(CP(D2D_N3GTDO), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtdo/\
				365	MUX_VAL(CP(D2D_N3GTMS), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtms/\
				366	MUX_VAL(CP(D2D_N3GTCK), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtck/\
				367	MUX_VAL(CP(D2D_N3GRTCK), (IEN \| PTD \| DIS \| M0)) /d2d_n3grtck/\
				368	MUX_VAL(CP(D2D_MSTDBY), (IEN \| PTU \| EN \| M0)) /d2d_mstdby/\
				369	MUX_VAL(CP(D2D_SWAKEUP), (IEN \| PTD \| EN \| M0)) /d2d_swakeup/\
				370	MUX_VAL(CP(D2D_IDLEREQ), (IEN \| PTD \| DIS \| M0)) /d2d_idlereq/\
				371	MUX_VAL(CP(D2D_IDLEACK), (IEN \| PTU \| EN \| M0)) /d2d_idleack/\
				372	MUX_VAL(CP(D2D_MWRITE), (IEN \| PTD \| DIS \| M0)) /d2d_mwrite/\
				373	MUX_VAL(CP(D2D_SWRITE), (IEN \| PTD \| DIS \| M0)) /d2d_swrite/\
				374	MUX_VAL(CP(D2D_MREAD), (IEN \| PTD \| DIS \| M0)) /d2d_mread/\
				375	MUX_VAL(CP(D2D_SREAD), (IEN \| PTD \| DIS \| M0)) /d2d_sread/\
				376	MUX_VAL(CP(D2D_MBUSFLAG), (IEN \| PTD \| DIS \| M0)) /d2d_mbusflag/\
				377	MUX_VAL(CP(D2D_SBUSFLAG), (IEN \| PTD \| DIS \| M0)) /d2d_sbusflag/\
				378	MUX_VAL(CP(SDRC_CKE0), (IDIS \| PTU \| EN \| M0)) /sdrc_cke0/\
				379	MUX_VAL(CP(SDRC_CKE1), (IDIS \| PTU \| EN \| M0)) /sdrc_cke1/
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	380
Steve Sakoman	a06e162	2010-08-24 10:37:29 -0700	[diff] [blame]	381	#define MUX_OVERO_SDIO2_DIRECT() \
				382	MUX_VAL(CP(MMC2_CLK), (IEN \| PTU \| EN \| M0)) /MMC2_CLK/\
				383	MUX_VAL(CP(MMC2_CMD), (IEN \| PTU \| EN \| M0)) /MMC2_CMD/\
				384	MUX_VAL(CP(MMC2_DAT0), (IEN \| PTU \| EN \| M0)) /MMC2_DAT0/\
				385	MUX_VAL(CP(MMC2_DAT1), (IEN \| PTU \| EN \| M0)) /MMC2_DAT1/\
				386	MUX_VAL(CP(MMC2_DAT2), (IEN \| PTU \| EN \| M0)) /MMC2_DAT2/\
				387	MUX_VAL(CP(MMC2_DAT3), (IEN \| PTU \| EN \| M0)) /MMC2_DAT3/\
				388	MUX_VAL(CP(MMC2_DAT4), (IEN \| PTU \| EN \| M0)) /MMC2_DAT4/\
				389	MUX_VAL(CP(MMC2_DAT5), (IEN \| PTU \| EN \| M0)) /MMC2_DAT5/\
				390	MUX_VAL(CP(MMC2_DAT6), (IEN \| PTU \| EN \| M0)) /MMC2_DAT6/\
				391	MUX_VAL(CP(MMC2_DAT7), (IEN \| PTU \| EN \| M0)) /MMC2_DAT7/\
				392	MUX_VAL(CP(MMC1_DAT4), (IEN \| PTD \| EN \| M4)) /GPIO_126/\
				393	MUX_VAL(CP(MMC1_DAT5), (IEN \| PTU \| EN \| M4)) /GPIO_127/\
				394	MUX_VAL(CP(MMC1_DAT6), (IEN \| PTU \| EN \| M4)) /GPIO_128/\
				395	MUX_VAL(CP(MMC1_DAT7), (IEN \| PTU \| EN \| M4)) /GPIO_129/
				396
				397	#define MUX_OVERO_SDIO2_TRANSCEIVER() \
				398	MUX_VAL(CP(MMC2_CLK), (IEN \| PTU \| EN \| M0)) /MMC2_CLK/\
				399	MUX_VAL(CP(MMC2_CMD), (IEN \| PTU \| EN \| M0)) /MMC2_CMD/\
				400	MUX_VAL(CP(MMC2_DAT0), (IEN \| PTU \| EN \| M0)) /MMC2_DAT0/\
				401	MUX_VAL(CP(MMC2_DAT1), (IEN \| PTU \| EN \| M0)) /MMC2_DAT1/\
				402	MUX_VAL(CP(MMC2_DAT2), (IEN \| PTU \| EN \| M0)) /MMC2_DAT2/\
				403	MUX_VAL(CP(MMC2_DAT3), (IEN \| PTU \| EN \| M0)) /MMC2_DAT3/\
				404	MUX_VAL(CP(MMC2_DAT4), (IEN \| PTU \| EN \| M1)) /MMC2_DIR_DAT0/\
				405	MUX_VAL(CP(MMC2_DAT5), (IEN \| PTU \| EN \| M1)) /MMC2_DIR_DAT1/\
				406	MUX_VAL(CP(MMC2_DAT6), (IEN \| PTU \| EN \| M1)) /MMC2_DIR_CMD/\
				407	MUX_VAL(CP(MMC2_DAT7), (IEN \| PTU \| EN \| M1)) /MMC2_CLKIN/\
				408	MUX_VAL(CP(MMC1_DAT4), (IEN \| PTU \| EN \| M4)) /GPIO_126/\
				409	MUX_VAL(CP(MMC1_DAT5), (IEN \| PTU \| EN \| M4)) /GPIO_127/\
				410	MUX_VAL(CP(MMC1_DAT6), (IEN \| PTU \| EN \| M4)) /GPIO_128/\
				411	MUX_VAL(CP(MMC1_DAT7), (IEN \| PTU \| EN \| M4)) /GPIO_129/
Olof Johansson	df38262	2009-09-29 10:22:45 -0400	[diff] [blame]	412
Steve Sakoman	d64b5b8	2010-09-20 08:05:14 -0700	[diff] [blame]	413	#define MUX_USRP_E() \
				414	MUX_VAL(CP(MCSPI1_SOMI), (IEN \| PTD \| DIS \| M4)) /GPIO_173 /\
				415	MUX_VAL(CP(MCSPI1_CS1), (IDIS \| PTD \| EN \| M4)) /GPIO_175 /\
				416
Dirk Behme	9d0fc81	2009-01-28 21:39:57 +0100	[diff] [blame]	417	#endif