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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Phil Edworthy7fbeb642011-06-01 07:35:13 +01002/*
Phil Edworthyefa4e1b2011-06-09 16:22:43 +01003 * Configuation settings for the Renesas RSK2+SH7264 board
Phil Edworthy7fbeb642011-06-01 07:35:13 +01004 *
5 * Copyright (C) 2011 Renesas Electronics Europe Ltd.
6 * Copyright (C) 2008 Nobuhiro Iwamatsu
7 * Copyright (C) 2008 Renesas Solutions Corp.
Phil Edworthy7fbeb642011-06-01 07:35:13 +01008 */
9
10#ifndef __RSK7264_H
11#define __RSK7264_H
12
Phil Edworthy7fbeb642011-06-01 07:35:13 +010013#define CONFIG_CPU_SH7264 1
Phil Edworthy7fbeb642011-06-01 07:35:13 +010014
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020015#define CONFIG_DISPLAY_BOARDINFO
16
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010017#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
Phil Edworthy7fbeb642011-06-01 07:35:13 +010018
Phil Edworthy7fbeb642011-06-01 07:35:13 +010019#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010020
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010021/* Serial */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010022#define CONFIG_CONS_SCIF3 1
23
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010024/* Memory */
25/* u-boot relocated to top 256KB of ram */
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010026#define CONFIG_SYS_SDRAM_BASE 0x0C000000
Phil Edworthy7fbeb642011-06-01 07:35:13 +010027#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
28
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010029#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
30#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010031#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010032#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
33#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010034
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010035/* Flash */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010036#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010037#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010038#define CONFIG_SYS_MAX_FLASH_BANKS 1
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010039#define CONFIG_SYS_MAX_FLASH_SECT 512
Phil Edworthy7fbeb642011-06-01 07:35:13 +010040
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010041#define CONFIG_ENV_OFFSET (128 * 1024)
42#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010043#define CONFIG_ENV_SECT_SIZE (128 * 1024)
44#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Phil Edworthy7fbeb642011-06-01 07:35:13 +010045
46/* Board Clock */
Phil Edworthy117029c2012-02-13 02:03:50 +000047#define CONFIG_SYS_CLK_FREQ 36000000
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090048#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010049#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
Nobuhiro Iwamatsu8f0960e2014-01-08 14:57:30 +090050#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010051
Phil Edworthy7fbeb642011-06-01 07:35:13 +010052#endif /* __RSK7264_H */